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| author | Angel Pons <th3fanbus@gmail.com> | 2021-12-18 13:16:06 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-12-19 22:52:13 +0000 |
| commit | 6ebb3b60a451b094376ddeff1c3b7b405190f62d (patch) | |
| tree | 72ec7d641056d53a119f7e40eb403936dd158d11 /src/mainboard/google/glados/variants/asuka/include/variant/gpio.h | |
| parent | 52ad86693999dc1544f0568ad75efbc0e44b15cc (diff) | |
| download | coreboot-6ebb3b60a451b094376ddeff1c3b7b405190f62d.tar.gz coreboot-6ebb3b60a451b094376ddeff1c3b7b405190f62d.tar.bz2 coreboot-6ebb3b60a451b094376ddeff1c3b7b405190f62d.zip | |
mainboard: Fix comment about early GPIOs
These boards program the early GPIO table in bootblock, not romstage.
Change-Id: Iae9353d106483f30cefa2d035d96e63e4c127261
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Sean Rhodes <admin@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/mainboard/google/glados/variants/asuka/include/variant/gpio.h')
| -rw-r--r-- | src/mainboard/google/glados/variants/asuka/include/variant/gpio.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h index d21d9e756ae3..3ee5532e4687 100644 --- a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h @@ -214,7 +214,7 @@ static const struct pad_config gpio_table[] = { /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock. */ static const struct pad_config early_gpio_table[] = { /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), |