diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2020-03-31 13:10:52 -0500 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@gmail.com> | 2020-04-03 16:23:18 +0000 |
| commit | e7dc4f40ef2220649e0c9a9872941a23fba3c18e (patch) | |
| tree | 7c81cd5cd262e3bd33104eb5ee29460a09ed0952 /src/mainboard/google/glados/variants/cave | |
| parent | d957d12e6dbf2eb912904f8cda7f9138a2ac314e (diff) | |
| download | coreboot-e7dc4f40ef2220649e0c9a9872941a23fba3c18e.tar.gz coreboot-e7dc4f40ef2220649e0c9a9872941a23fba3c18e.tar.bz2 coreboot-e7dc4f40ef2220649e0c9a9872941a23fba3c18e.zip | |
mb/google/glados: drop VR configs from devicetree
The VR config values used in the variants' devicetrees is
identical to the domain defaults in vr_config.c, with the
exception of the icc_max value, which is calculated dynamically
based on SKU, and again matches the default values for
each domain and each varaint.
Test: add a print function to dump the VR config values for each
domain from the UPDs after setting, verify same output before/after.
Change-Id: I4307f6e19ae6f99d4f5e475b181fd66c5b92f28c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39982
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/glados/variants/cave')
| -rw-r--r-- | src/mainboard/google/glados/variants/cave/devicetree.cb | 66 |
1 files changed, 0 insertions, 66 deletions
diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index 41bb82e053c7..ccc2302a58e5 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -70,72 +70,6 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains - #+----------------+-----------+-----------+-------------+----------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-----------+-----------+-------------+----------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 4A | 24A | 24A | 24A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-----------+-----------+-------------+----------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(4), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# |