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authorJulius Werner <jwerner@chromium.org>2016-07-28 13:41:37 -0700
committerMartin Roth <martinroth@google.com>2016-08-03 18:23:23 +0200
commit40d62f3db7c77bc4d48d3a584ac607b348c44d8c (patch)
treeaa6edc29645fd42753b39045bd6c2d69dc96631c /src/mainboard/google/gru/bootblock.c
parent5e6771b1cb2ee4f12c7991e04c0f0f9acf9c3e0a (diff)
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google/gru: Add code to support I2C TPM for Kevin
Coming Kevin revisions will switch back to an I2C TPM. This patch adds the required configuration options and code to support that. Since the TPM type can currently only be changed at compile time, we can no longer support older Kevins with the same image. In order to build for Kevin revisions < 5, you have to explicitly override the CONFIG_GRU_HAS_TPM2. BRANCH=None BUG=chrome-os-partner:55523 TEST=Compiled both Kevin and Gru, confirmed that bootblock and verstage binary had the appropriate code differences. Change-Id: I1b2abe0f331eb103eb0a84f773ee7521d31ae5d8 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3245bff937154f0f9f39894de9c98a75631d59d9 Original-Change-Id: I81a15c9fb037a7ca2d69818e46cbb4f9a5ae1989 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/364222 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16029 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/gru/bootblock.c')
-rw-r--r--src/mainboard/google/gru/bootblock.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index 20334953a1bc..8f88043f9225 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -18,6 +18,7 @@
#include <bootblock_common.h>
#include <soc/grf.h>
#include <gpio.h>
+#include <soc/i2c.h>
#include <soc/spi.h>
#include <console/console.h>
@@ -68,9 +69,16 @@ void bootblock_mainboard_init(void)
write32(&rk3399_grf->iomux_spi5, IOMUX_SPI5);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 3093750);
- /* Set pinmux and configure TPM SPI, which is not very fast. */
- write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz);
+ if (IS_ENABLED(CONFIG_GRU_HAS_TPM2)) {
+ /* Set pinmux and configure TPM SPI, which is not very fast. */
+ write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0);
+ rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz);
+ } else {
+ /* Set pinmux and configure TPM I2C */
+ write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL);
+ write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA);
+ i2c_init(0, 400*KHz);
+ }
setup_chromeos_gpios();
}