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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-05-25 20:51:35 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-27 15:39:17 +0000 |
| commit | a7c410b28602e337a85466429540663a7f3a219a (patch) | |
| tree | 26962759d6e17a2e12006ba9bcda9197ca23f4ee /src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | |
| parent | 9a24c3f80d477f304a966094ded1ccde4155375c (diff) | |
| download | coreboot-a7c410b28602e337a85466429540663a7f3a219a.tar.gz coreboot-a7c410b28602e337a85466429540663a7f3a219a.tar.bz2 coreboot-a7c410b28602e337a85466429540663a7f3a219a.zip | |
mb/google/guybrush: set PSPP policy to powersave
BUG=b:188793754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I262c4c3ae90d8d12fdfe71a3620739070a444a55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54931
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/guybrush/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 34540014ee68..18e7012abfe6 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -52,6 +52,8 @@ chip soc/amd/cezanne register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" + register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + register "usb_phy_custom" = "1" register "usb_phy" = "{ .Usb2PhyPort[0] = { |