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authorKarthikeyan Ramasubramanian <kramasub@chromium.org>2021-10-25 22:50:33 -0600
committerRaul Rangel <rrangel@chromium.org>2021-10-27 22:03:42 +0000
commit750abb1fe7ffcc9e90c60617cd42bb108a82168b (patch)
treec672063734618f21f5b5c38695c8974d64967cb3 /src/mainboard/google/guybrush
parent1bdf09d91aebbd4aca80fe9ee2a75368662f3dc6 (diff)
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mb/google/guybrush: Update SD_AUX_RESET_L signal
On all upcoming variants and board versions of existing variants, SD_AUX_RESET_L signal moves from GPIO_69 to GPIO_5. This means all boards except: * All board versions of Guybrush * Nipperkin Board Version 1. Also in Nipperkin, LCD_PRIVACY_PCH signal moves from GPIO_5 to GPIO_18. Configure the gpios accordingly in baseboard, guybrush and nipperkin variants accordingly. Also update the DXIO port descriptor for SD PCIe engine with the corresponding AUX reset GPIO. BUG=b:202992077 TEST=Build and boot to OS in Guybrush & Nipperkin. Ensure that the SD Controller and SD Card are enumerated fine. Ensure that the enumeration is successful after a suspend/resume cycle. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If28810747e6b4eaae2a693a98e1adc830f80bcf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
Diffstat (limited to 'src/mainboard/google/guybrush')
-rw-r--r--src/mainboard/google/guybrush/port_descriptors.c3
-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/gpio.c24
-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/helpers.c6
-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h2
-rw-r--r--src/mainboard/google/guybrush/variants/guybrush/gpio.c27
-rw-r--r--src/mainboard/google/guybrush/variants/guybrush/variant.c6
-rw-r--r--src/mainboard/google/guybrush/variants/nipperkin/gpio.c54
-rw-r--r--src/mainboard/google/guybrush/variants/nipperkin/variant.c9
8 files changed, 107 insertions, 24 deletions
diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c
index cf8153412a04..a98983b6bce2 100644
--- a/src/mainboard/google/guybrush/port_descriptors.c
+++ b/src/mainboard/google/guybrush/port_descriptors.c
@@ -127,6 +127,9 @@ void mainboard_get_dxio_ddi_descriptors(
const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
{
+ /* Get Variant specific SD AUX Reset GPIO */
+ guybrush_czn_dxio_descriptors[SD].gpio_group_id = variant_sd_aux_reset_gpio();
+
/* gpp_bridge_2 is used either for WWAN or NVME bridge. Mark it as PCIE_ENGINE when it
is enabled. */
if (is_dev_enabled(DEV_PTR(gpp_bridge_2)))
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index 376cf4ab0d05..c45d3a78ce69 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -21,8 +21,8 @@ static const struct soc_amd_gpio base_gpio_table[] = {
PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
/* SOC_PEN_DETECT_ODL */
PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S0i3),
- /* Unused */
- PAD_NC(GPIO_5),
+ /* SD_AUX_RESET_L */
+ PAD_GPO(GPIO_5, HIGH),
/* EN_PP3300_WLAN */
PAD_GPO(GPIO_6, HIGH),
/* EN_PP3300_TCHPAD */
@@ -81,8 +81,8 @@ static const struct soc_amd_gpio base_gpio_table[] = {
PAD_GPI(GPIO_67, PULL_NONE),
/* EN_PP3300_TCHSCR */
PAD_GPO(GPIO_68, HIGH),
- /* SD_AUX_RESET_L */
- PAD_GPO(GPIO_69, HIGH),
+ /* Unused */
+ PAD_NC(GPIO_69),
/* Unused TP27 */
PAD_NC(GPIO_70),
/* GPIO_71 - GPIO_73: Not available */
@@ -170,15 +170,17 @@ static const struct soc_amd_gpio base_gpio_table[] = {
/* Early GPIO configuration */
static const struct soc_amd_gpio early_gpio_table[] = {
/* Assert all AUX reset lines */
+ /* SD_AUX_RESET_L */
+ PAD_GPO(GPIO_5, LOW),
/* WWAN_AUX_RESET_L */
PAD_GPO(GPIO_18, LOW),
/* WLAN_AUX_RESET (ACTIVE HIGH) */
PAD_GPO(GPIO_29, HIGH),
/* SSD_AUX_RESET_L */
PAD_GPO(GPIO_40, LOW),
- /* SD_AUX_RESET_L */
- PAD_GPO(GPIO_69, LOW),
- /* Guybrush BID>1: Unused TP27; BID==1: SD_AUX_RESET_L */
+ /* Guybrush BID >= 2: SD_AUX_RESET_L, Other variants: Unused */
+ PAD_NC(GPIO_69),
+ /* Guybrush BID>1, Other variants : Unused TP27; BID==1: SD_AUX_RESET_L */
PAD_NC(GPIO_70),
/* Deassert PCIe Reset lines */
@@ -275,15 +277,17 @@ static const struct soc_amd_gpio sleep_gpio_table[] = {
/* PCIE_RST needs to be brought high before FSP-M runs */
static const struct soc_amd_gpio pcie_gpio_table[] = {
/* Deassert all AUX_RESET lines & PCIE_RST */
+ /* SD_AUX_RESET_L */
+ PAD_GPO(GPIO_5, HIGH),
/* WWAN_AUX_RESET_L */
PAD_GPO(GPIO_18, HIGH),
/* WLAN_AUX_RESET (ACTIVE HIGH) */
PAD_GPO(GPIO_29, LOW),
/* SSD_AUX_RESET_L */
PAD_GPO(GPIO_40, HIGH),
- /* SD_AUX_RESET_L */
- PAD_GPO(GPIO_69, HIGH),
- /* BID>1: Unused TP27; BID==1: SD_AUX_RESET_L */
+ /* Guybrush BID >= 2: SD_AUX_RESET_L, Other variants: Unused */
+ PAD_NC(GPIO_69),
+ /* Guybrush BID>1, Other variants : Unused TP27; BID==1: SD_AUX_RESET_L */
PAD_NC(GPIO_70),
/* PCIE_RST0_L */
PAD_NFO(GPIO_26, PCIE_RST_L, HIGH),
diff --git a/src/mainboard/google/guybrush/variants/baseboard/helpers.c b/src/mainboard/google/guybrush/variants/baseboard/helpers.c
index 248e7a98ab84..04c05bbcc14c 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/helpers.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/helpers.c
@@ -2,6 +2,7 @@
#include <baseboard/variants.h>
#include <device/device.h>
+#include <soc/gpio.h>
WEAK_DEV_PTR(fpmcu);
@@ -14,3 +15,8 @@ bool __weak variant_has_pcie_wwan(void)
{
return false;
}
+
+uint8_t __weak variant_sd_aux_reset_gpio(void)
+{
+ return GPIO_5;
+}
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
index eabce1f4cdc8..84e3d3964486 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
@@ -58,4 +58,6 @@ enum dxio_port_id {
NVME
};
+uint8_t variant_sd_aux_reset_gpio(void);
+
#endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
index fa3a8226f9cc..886c1cc9b7a8 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c
+++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
@@ -25,21 +25,32 @@ static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = {
static const struct soc_amd_gpio bid2_ramstage_gpio_table[] = {
/* EN_PP5000_PEN */
PAD_GPO(GPIO_5, HIGH),
+ /* SD_AUX_RESET_L */
+ PAD_GPO(GPIO_69, HIGH),
};
-/* This table is used by guybrush variant with board version < 2. */
-/* Use AUX Reset lines instead of PCIE_RST for Board Version 1 */
static const struct soc_amd_gpio override_early_gpio_table[] = {
- /* SD_AUX_RESET_L */
+ PAD_NC(GPIO_5),
+ /* BID >= 2: SD_AUX_RESET_L */
+ PAD_GPO(GPIO_69, LOW),
+ /* BID == 1: SD_AUX_RESET_L */
PAD_GPO(GPIO_70, LOW),
};
/* This table is used by guybrush variant with board version < 2. */
static const struct soc_amd_gpio bid1_pcie_gpio_table[] = {
+ PAD_NC(GPIO_5),
/* SD_AUX_RESET_L */
PAD_GPO(GPIO_70, HIGH),
};
+/* This table is used by guybrush variant with board version < 2. */
+static const struct soc_amd_gpio bid2_pcie_gpio_table[] = {
+ PAD_NC(GPIO_5),
+ /* SD_AUX_RESET_L */
+ PAD_GPO(GPIO_69, HIGH),
+};
+
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
{
uint32_t board_version = board_id();
@@ -58,10 +69,8 @@ const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
{
/*
* This code is run before the EC is available to check the board ID
- * since this is needed to work on Board ID 1 and is unused on other
- * versions of guybrush, just enable it.
- *
- * Guybrush BID>1: Unused TP27; BID==1: SD_AUX_RESET_L
+ * since this is needed to work on all versions of guybrush, just enable
+ * both GPIOs and reconfigure them on later stages.
*/
*size = ARRAY_SIZE(override_early_gpio_table);
return override_early_gpio_table;
@@ -75,5 +84,7 @@ const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size)
*size = ARRAY_SIZE(bid1_pcie_gpio_table);
return bid1_pcie_gpio_table;
}
- return NULL;
+
+ *size = ARRAY_SIZE(bid2_pcie_gpio_table);
+ return bid2_pcie_gpio_table;
}
diff --git a/src/mainboard/google/guybrush/variants/guybrush/variant.c b/src/mainboard/google/guybrush/variants/guybrush/variant.c
index cde24cb9c065..ded135167422 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/variant.c
+++ b/src/mainboard/google/guybrush/variants/guybrush/variant.c
@@ -2,8 +2,14 @@
#include <baseboard/variants.h>
#include <device/device.h>
+#include <soc/gpio.h>
bool variant_has_pcie_wwan(void)
{
return is_dev_enabled(DEV_PTR(gpp_bridge_2));
}
+
+uint8_t variant_sd_aux_reset_gpio(void)
+{
+ return GPIO_69;
+}
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c
index 31fedad66a1b..2699f2a1cf6e 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c
+++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c
@@ -2,11 +2,13 @@
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
+#include <boardid.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <baseboard/variants.h>
-static const struct soc_amd_gpio override_gpio_table[] = {
+/* This table is used by nipperkin variant with board version < 2. */
+static const struct soc_amd_gpio bid1_override_gpio_table[] = {
/* Unused TP1056 */
PAD_NC(GPIO_4),
/* Unused TP1063 */
@@ -14,20 +16,53 @@ static const struct soc_amd_gpio override_gpio_table[] = {
PAD_NC(GPIO_18),
/* LCD_PRIVACY_PCH */
PAD_GPO(GPIO_5, HIGH),
+ /* SD_AUX_RESET_L */
+ PAD_GPO(GPIO_69, HIGH),
+};
+
+/* This table is used by nipperkin variant with board version >= 2. */
+static const struct soc_amd_gpio bid2_override_gpio_table[] = {
+ /* Unused TP1056 */
+ PAD_NC(GPIO_4),
+ /* Unused TP1063 */
+ PAD_NC(GPIO_17),
+ /* LCD_PRIVACY_PCH */
+ PAD_GPO(GPIO_18, HIGH),
+ /* Unused */
+ PAD_NC(GPIO_69),
};
static const struct soc_amd_gpio override_early_gpio_table[] = {
PAD_NC(GPIO_18),
+ /* SD_AUX_RESET_L */
+ PAD_GPO(GPIO_69, LOW),
};
-static const struct soc_amd_gpio override_pcie_gpio_table[] = {
+/* This table is used by nipperkin variant with board version < 2. */
+static const struct soc_amd_gpio bid1_override_pcie_gpio_table[] = {
+ PAD_NC(GPIO_5),
PAD_NC(GPIO_18),
+ /* SD_AUX_RESET_L */
+ PAD_GPO(GPIO_69, HIGH),
+};
+
+/* This table is used by nipperkin variant with board version >= 2. */
+static const struct soc_amd_gpio bid2_override_pcie_gpio_table[] = {
+ PAD_NC(GPIO_18),
+ PAD_NC(GPIO_69),
};
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
{
- *size = ARRAY_SIZE(override_gpio_table);
- return override_gpio_table;
+ uint32_t board_version = board_id();
+
+ if (board_version < 2) {
+ *size = ARRAY_SIZE(bid1_override_gpio_table);
+ return bid1_override_gpio_table;
+ }
+
+ *size = ARRAY_SIZE(bid2_override_gpio_table);
+ return bid2_override_gpio_table;
}
const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
@@ -38,6 +73,13 @@ const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size)
{
- *size = ARRAY_SIZE(override_pcie_gpio_table);
- return override_pcie_gpio_table;
+ uint32_t board_version = board_id();
+
+ if (board_version < 2) {
+ *size = ARRAY_SIZE(bid1_override_pcie_gpio_table);
+ return bid1_override_pcie_gpio_table;
+ }
+
+ *size = ARRAY_SIZE(bid2_override_pcie_gpio_table);
+ return bid2_override_pcie_gpio_table;
}
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/variant.c b/src/mainboard/google/guybrush/variants/nipperkin/variant.c
index 3315fa0249bf..917857c3ac15 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/variant.c
+++ b/src/mainboard/google/guybrush/variants/nipperkin/variant.c
@@ -1,10 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
+#include <boardid.h>
#include <device/device.h>
+#include <soc/gpio.h>
void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors)
{
dxio_descriptors[WLAN].link_aspm_L1_1 = false;
dxio_descriptors[WLAN].link_aspm_L1_2 = false;
}
+
+uint8_t variant_sd_aux_reset_gpio(void)
+{
+ uint32_t board_ver = board_id();
+
+ return (board_ver < 2) ? GPIO_69 : GPIO_5;
+}