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| author | Rob Barnes <robbarnes@google.com> | 2021-11-15 12:56:34 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-17 14:30:01 +0000 |
| commit | 847a39fec7eb6b63497c0f1b7df82c19c226e0a1 (patch) | |
| tree | a76c79fcc06145e64ff4f162e48b3bfb22c007dc /src/mainboard/google/guybrush | |
| parent | 1a4b132413cacadd17b66add6758d24036a1c283 (diff) | |
| download | coreboot-847a39fec7eb6b63497c0f1b7df82c19c226e0a1.tar.gz coreboot-847a39fec7eb6b63497c0f1b7df82c19c226e0a1.tar.bz2 coreboot-847a39fec7eb6b63497c0f1b7df82c19c226e0a1.zip | |
soc/amd/psp_verstage: Split up verstage_soc_init
Make psp verstage initialization more granular be splitting
verstage_soc_init into separate functions. Specifically, create
soc init functions for espi, i2c spi, and aoac.
BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush
Change-Id: I489889a0dfd4016aa4f2b53a2c6a7a1ea4459e60
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/mainboard/google/guybrush')
0 files changed, 0 insertions, 0 deletions