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| author | Jon Murphy <jpmurphy@google.com> | 2022-05-20 14:19:36 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-07 12:39:24 +0000 |
| commit | f658b3588904737b1641bd1664dd17e9a6805237 (patch) | |
| tree | 2ec24476bf660f325ca36670699ec7c010728277 /src/mainboard/google/guybrush | |
| parent | 23d24657209d810d39a16c561ea1f68f98f8237b (diff) | |
| download | coreboot-f658b3588904737b1641bd1664dd17e9a6805237.tar.gz coreboot-f658b3588904737b1641bd1664dd17e9a6805237.tar.bz2 coreboot-f658b3588904737b1641bd1664dd17e9a6805237.zip | |
mb/google/guybrush: Remove TODO's and update text
Remove TODO's for dummy DXIO descriptors, update comment
to reflect what they are. These devices are needed for the
platform to function properly. Also remove the TODO for
DDI descriptors as they are functioning correctly.
BUG=b:232952508
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I1535c08cac3f0bcb30061aba2aa593eb22109387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard/google/guybrush')
| -rw-r--r-- | src/mainboard/google/guybrush/port_descriptors.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index 040298b92d6d..b2a7e644695d 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -70,7 +70,7 @@ static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .clk_req = CLK_REQ3, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, - { /* TODO: remove this temporary workaround */ + { /* Dummy Device */ .engine_type = PCIE_ENGINE, .port_present = true, .start_logical_lane = 8, @@ -81,7 +81,7 @@ static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .clk_req = CLK_REQ5, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, - { /* TODO: remove this temporary workaround */ + { /* Dummy Device */ .engine_type = PCIE_ENGINE, .port_present = true, .start_logical_lane = 16, @@ -94,7 +94,6 @@ static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { } }; -/* TODO: verify the DDI table, since this is mostly an educated guess right now */ static fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = { { /* DDI0 - eDP */ .connector_type = DDI_EDP, |