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authorShelley Chen <shchen@google.com>2018-12-10 12:59:01 -0800
committerShelley Chen <shchen@google.com>2018-12-13 00:46:09 +0000
commite3110b862071ae0797afb0688495315a7dd47739 (patch)
treed7741f2bdd16e41746503e2db3e5f3a60929c843 /src/mainboard/google/hatch/chromeos.c
parent4ba64c99e3afc7689eab1f498134c43d40248d25 (diff)
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mb/google/hatch: Creating skeleton directories and files
Creating skeleton files and directories in mainboard for the new Hatch board. This is to facilitate development for different parties involved. BUG=None BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/mainboard/google/hatch/chromeos.c')
-rw-r--r--src/mainboard/google/hatch/chromeos.c80
1 files changed, 80 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c
new file mode 100644
index 000000000000..36fba45ac79c
--- /dev/null
+++ b/src/mainboard/google/hatch/chromeos.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
+#include <variant/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ {-1, ACTIVE_HIGH, 0, "EC in RW"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+static int cros_get_gpio_value(int type)
+{
+ const struct cros_gpio *cros_gpios;
+ size_t i, num_gpios = 0;
+
+ cros_gpios = variant_cros_gpios(&num_gpios);
+
+ for (i = 0; i < num_gpios; i++) {
+ const struct cros_gpio *gpio = &cros_gpios[i];
+ if (gpio->type == type) {
+ int state = gpio_get(gpio->gpio_num);
+ if (gpio->polarity == CROS_GPIO_ACTIVE_LOW)
+ return !state;
+ else
+ return state;
+ }
+ }
+ return 0;
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ const struct cros_gpio *cros_gpios;
+ size_t num_gpios = 0;
+
+ cros_gpios = variant_cros_gpios(&num_gpios);
+
+ chromeos_acpi_gpio_generate(cros_gpios, num_gpios);
+}
+
+int get_write_protect_state(void)
+{
+ return cros_get_gpio_value(CROS_GPIO_WP);
+}
+
+int get_recovery_mode_switch(void)
+{
+ return cros_get_gpio_value(CROS_GPIO_REC);
+}
+
+int get_lid_switch(void)
+{
+ return 1;
+}