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authorShelley Chen <shchen@google.com>2018-12-10 12:59:01 -0800
committerShelley Chen <shchen@google.com>2018-12-13 00:46:09 +0000
commite3110b862071ae0797afb0688495315a7dd47739 (patch)
treed7741f2bdd16e41746503e2db3e5f3a60929c843 /src/mainboard/google/hatch/ramstage.c
parent4ba64c99e3afc7689eab1f498134c43d40248d25 (diff)
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mb/google/hatch: Creating skeleton directories and files
Creating skeleton files and directories in mainboard for the new Hatch board. This is to facilitate development for different parties involved. BUG=None BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/mainboard/google/hatch/ramstage.c')
-rw-r--r--src/mainboard/google/hatch/ramstage.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c
new file mode 100644
index 000000000000..1ac6a296cd94
--- /dev/null
+++ b/src/mainboard/google/hatch/ramstage.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <soc/ramstage.h>
+#include <variant/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ const struct pad_config *gpio_table;
+ size_t num_gpios;
+
+ gpio_table = variant_base_gpio_table(&num_gpios);
+ gpio_configure_pads(gpio_table, num_gpios);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};