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author | Matt DeVillier <matt.devillier@gmail.com> | 2022-09-07 17:21:01 -0500 |
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committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-09-22 15:35:19 +0000 |
commit | 45b1da33c80a4b1328794a5a59c93d1988cee4f1 (patch) | |
tree | 7f7c7c6b7c44632c72b2a5bc717f74bcf678f7c8 /src/mainboard/google/hatch/romstage.c | |
parent | 826b45b69b9dd492771798679d3a8223a954217f (diff) | |
download | coreboot-45b1da33c80a4b1328794a5a59c93d1988cee4f1.tar.gz coreboot-45b1da33c80a4b1328794a5a59c93d1988cee4f1.tar.bz2 coreboot-45b1da33c80a4b1328794a5a59c93d1988cee4f1.zip |
mb/google/hatch: split up hatch and puff baseboards
The hatch and puff baseboards have diverged enough to where it makes
more sense to split them into separate boards. Copy the mb/google/hatch
directory into a new dir 'puff' and strip out all boards and items
related to the hatch baseboard. Remove all puff-related items from the
original hatch directory. Clean up and alphabetize Kconfig selections.
Test: build and boot akemi hatch variant and wyvern puff variant.
Change-Id: I8c7350f3afcff3ddefc6fa14054a3f9257568cd3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62970
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/romstage.c')
-rw-r--r-- | src/mainboard/google/hatch/romstage.c | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c new file mode 100644 index 000000000000..eb5153c1339b --- /dev/null +++ b/src/mainboard/google/hatch/romstage.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> +#include <gpio.h> +#include <memory_info.h> +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <variant/gpio.h> + +/* + * GPIO_MEM_CH_SEL is set to 1 for single channel skus + * and 0 for dual channel skus. + */ +#define GPIO_MEM_CH_SEL GPP_F2 + +int __weak variant_memory_sku(void) +{ + const gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + struct cnl_mb_cfg memcfg; + int mem_sku; + int is_single_ch_mem; + + variant_memory_params(&memcfg); + mem_sku = variant_memory_sku(); + /* + * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single + * channel skus and 0 for dual channel skus. + */ + is_single_ch_mem = gpio_get(GPIO_MEM_CH_SEL); + + /* + * spd[0]-spd[3] map to CH0D0, CH0D1, CH1D0, CH1D1 respectively. + * Dual-DIMM memory is not used in hatch family, so we only + * fill in spd_info for CH0D0 and CH1D0 here. + */ + memcfg.spd[0].read_type = READ_SPD_CBFS; + memcfg.spd[0].spd_spec.spd_index = mem_sku; + if (!is_single_ch_mem) { + memcfg.spd[2].read_type = READ_SPD_CBFS; + memcfg.spd[2].spd_spec.spd_index = mem_sku; + } + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} |