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| author | Peter Marheine <pmarheine@chromium.org> | 2020-04-20 13:53:47 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-04-21 01:24:01 +0000 |
| commit | c5028b2e86fa58c7c7a5e1e47e8654b79a0c0e0c (patch) | |
| tree | 0f5f21a3d455a672fbf39478e5dfe243ac23ac28 /src/mainboard/google/hatch/variants/duffy/overridetree.cb | |
| parent | 962c788861dc4d36d9e3d7a3c238e746e7dc146f (diff) | |
| download | coreboot-c5028b2e86fa58c7c7a5e1e47e8654b79a0c0e0c.tar.gz coreboot-c5028b2e86fa58c7c7a5e1e47e8654b79a0c0e0c.tar.bz2 coreboot-c5028b2e86fa58c7c7a5e1e47e8654b79a0c0e0c.zip | |
mb/google/puff: configure USB PLD groups
Each physical port should have the same group and position for both USB2
and USB3, but puff and its variants use different layout than the
baseboard so they must override PLD.
Ports are split into two groups for front and back, with positions in
each group numbered from left to right.
BUG=b:151579409
BRANCH=none
TEST=PLD_GroupToken and PLD_GroupPosition are set as expected in SSDT.
Change-Id: Ibe19e4faa1fbc7117687d789e9bd5584852a48c0
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google/hatch/variants/duffy/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/hatch/variants/duffy/overridetree.cb | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index 3507e6d5ebf9..2f36bc8b62c8 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -191,31 +191,37 @@ chip soc/intel/cannonlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" device usb 2.0 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port Rear"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" device usb 2.1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Right"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" device usb 2.2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Rear Right"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" device usb 2.3 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Rear Middle"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 2.4 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Rear Left"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" device usb 2.5 on end end chip drivers/usb/acpi @@ -224,31 +230,37 @@ chip soc/intel/cannonlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Front Left"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" device usb 3.0 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Front Right"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" device usb 3.1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Rear Right"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" device usb 3.2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Rear"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" device usb 3.3 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Rear Left"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" device usb 3.4 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Rear Middle"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 3.5 on end end end |