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| author | Wisley Chen <wisley.chen@quantatw.com> | 2019-11-08 23:51:00 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-20 13:32:08 +0000 |
| commit | 3bc70228a2edbf9ee4283515307d8d44dd512192 (patch) | |
| tree | 66f4b965624b808757684d2a26a67390c552c9c9 /src/mainboard/google/hatch/variants/jinlon/Makefile.inc | |
| parent | f2cae5085c49904b827d867dbf8d1a8b0d284c74 (diff) | |
| download | coreboot-3bc70228a2edbf9ee4283515307d8d44dd512192.tar.gz coreboot-3bc70228a2edbf9ee4283515307d8d44dd512192.tar.bz2 coreboot-3bc70228a2edbf9ee4283515307d8d44dd512192.zip | |
/mb/google/hatch: Create jinlon variant
Create new variant for jinlon
BUG=b:144150654
TEST=emerge-hatch coreboot chromeos-bootimage and boot on jinlon proto
board
Change-Id: I8deb29041475e38cbbf2f54519940f62b9f21822
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36681
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/variants/jinlon/Makefile.inc')
| -rw-r--r-- | src/mainboard/google/hatch/variants/jinlon/Makefile.inc | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc new file mode 100644 index 000000000000..6e5d8835dbb0 --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc @@ -0,0 +1,27 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 +SPD_SOURCES += 8G_3200 # 0b110 +SPD_SOURCES += 16G_3200 # 0b111 +SPD_SOURCES += 16G_2666_2bg # 0b1000 +SPD_SOURCES += 16G_3200_4bg # 0b1001 + +bootblock-y += gpio.c +ramstage-y += gpio.c |