summaryrefslogtreecommitdiffstats
path: root/src/mainboard/google/hatch
diff options
context:
space:
mode:
authorKenneth Chan <kenneth.chan@quanta.corp-partner.google.com>2022-01-06 16:42:48 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-01-10 14:19:53 +0000
commit9b9fe92e28cd8dba55ad08fa64aeb30f24dcef95 (patch)
tree8b994ff55eb7d2ba5d1a6ec2421ba2e57a33dd5f /src/mainboard/google/hatch
parentda3edab901988821dbc518ccdcb06ff933940f31 (diff)
downloadcoreboot-9b9fe92e28cd8dba55ad08fa64aeb30f24dcef95.tar.gz
coreboot-9b9fe92e28cd8dba55ad08fa64aeb30f24dcef95.tar.bz2
coreboot-9b9fe92e28cd8dba55ad08fa64aeb30f24dcef95.zip
mb/google/hatch/var/scout: Update DPTF parameters
Update the DPTF parameters received from the thermal team. Refer to https://partnerissuetracker.corp.google.com/issues/195602767#comment6. BUG=b:195602767 TEST=emerge-ambassador coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I93fe388ff1862d0a96b11ce68a5d28664f11996a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/hatch')
-rw-r--r--src/mainboard/google/hatch/variants/scout/overridetree.cb10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/hatch/variants/scout/overridetree.cb b/src/mainboard/google/hatch/variants/scout/overridetree.cb
index 07c64dbbe1e7..1312966189ff 100644
--- a/src/mainboard/google/hatch/variants/scout/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/scout/overridetree.cb
@@ -241,12 +241,12 @@ chip soc/intel/cannonlake
register "policies.active[0]" = "{.target=DPTF_CPU,
.thresholds={TEMP_PCT(94, 0),}}"
register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
- .thresholds={TEMP_PCT(84, 90),
- TEMP_PCT(82, 80),
+ .thresholds={TEMP_PCT(82, 80),
TEMP_PCT(80, 70),
- TEMP_PCT(66, 60),
- TEMP_PCT(52, 50),
- TEMP_PCT(35, 40),}}"
+ TEMP_PCT(78, 60),
+ TEMP_PCT(75, 50),
+ TEMP_PCT(73, 40),
+ TEMP_PCT(35, 30),}}"
## Passive Policy
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"