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| author | Jon Murphy <jpmurphy@google.com> | 2022-06-28 10:36:23 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-04 14:02:26 +0000 |
| commit | c4e90454f4e3787c9e5d0b7aa758ee9b5757df4b (patch) | |
| tree | ad1a49b4477d62eb6604e3332b6ffc4a64daed06 /src/mainboard/google/hatch | |
| parent | dc86804a7db0ac67b81803d1662608320c8838a7 (diff) | |
| download | coreboot-c4e90454f4e3787c9e5d0b7aa758ee9b5757df4b.tar.gz coreboot-c4e90454f4e3787c9e5d0b7aa758ee9b5757df4b.tar.bz2 coreboot-c4e90454f4e3787c9e5d0b7aa758ee9b5757df4b.zip | |
treewide: Unify Google branding
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/mainboard/google/hatch')
| -rw-r--r-- | src/mainboard/google/hatch/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/dsdt.asl | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 749b0df30afb..712ed06e7ccc 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -166,7 +166,7 @@ config CHROMEOS select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU config CHROMEOS_WIFI_SAR - bool "Enable SAR options for Chrome OS build" + bool "Enable SAR options for ChromeOS build" depends on CHROMEOS select DSAR_ENABLE select GEO_SAR_ENABLE diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 022a607a1df8..dad2267c338a 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -35,7 +35,7 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ |