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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-11-07 10:23:36 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-04-09 02:50:01 +0000 |
| commit | 7a874330919a4df9cc5b66058b4340465b7ea041 (patch) | |
| tree | 7192d50705fde0142ccc3747e712d6641329edd1 /src/mainboard/google/jecht/chromeos.c | |
| parent | 5619ea2b982003b23bdeb48890981605a6201d67 (diff) | |
| download | coreboot-7a874330919a4df9cc5b66058b4340465b7ea041.tar.gz coreboot-7a874330919a4df9cc5b66058b4340465b7ea041.tar.bz2 coreboot-7a874330919a4df9cc5b66058b4340465b7ea041.zip | |
mb/google,samsung: Drop init_bootmode_straps()
Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/jecht/chromeos.c')
| -rw-r--r-- | src/mainboard/google/jecht/chromeos.c | 39 |
1 files changed, 2 insertions, 37 deletions
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index d8ecb4e6529c..563e32b79cc6 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -6,15 +6,10 @@ #include <device/device.h> #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <ec/google/chromeec/ec.h> #include <soc/chromeos.h> -#include <soc/sata.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> #include "onboard.h" -#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -27,44 +22,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static bool raw_write_protect_state(void) -{ - return get_gpio(GPIO_SPI_WP); -} - -static bool raw_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - int get_write_protect_state(void) { - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; + return get_gpio(GPIO_SPI_WP); } int get_recovery_mode_switch(void) { - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - -void init_bootmode_straps(void) -{ - u32 flags = 0; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - - /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (raw_write_protect_state()) - flags |= (1 << FLAG_SPI_WP); - - /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (raw_recovery_mode_switch()) - flags |= (1 << FLAG_REC_MODE); - - /* Developer: Virtual */ - - pci_s_write_config32(dev, SATA_SP, flags); + return !get_gpio(GPIO_REC_MODE); } static const struct cros_gpio cros_gpios[] = { |