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| author | Matt DeVillier <matt.devillier@gmail.com> | 2016-12-17 17:13:23 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-12-22 18:37:35 +0100 |
| commit | 0148fcb4e1d1c4e43cd21e7b28a65afd762daa6d (patch) | |
| tree | 2d89da8657235d12119187671564b294ed07b83b /src/mainboard/google/jecht/romstage.c | |
| parent | 6390e525fcbad63fbf4c0043ae248b24b9a9d0c6 (diff) | |
| download | coreboot-0148fcb4e1d1c4e43cd21e7b28a65afd762daa6d.tar.gz coreboot-0148fcb4e1d1c4e43cd21e7b28a65afd762daa6d.tar.bz2 coreboot-0148fcb4e1d1c4e43cd21e7b28a65afd762daa6d.zip | |
Combine Broadwell Chromeboxes using variant board scheme
Combine existing boards google/guado, rikku, and tidus using
their common reference board google/jecht as a base.
Additional changes besides simple consolidation include:
- simplify power LED functions
- simplify HDA verb definitions using azelia macros
- use common SoC functions to generate FADT table
- correct FADT table header version
- remove unused haswell_pci_irqs.asl
- remove unused header includes (various)
- set sane default fan speed (0x4d) for all variants
Variant setup modeled after google/beltino
Change-Id: I77a2dffe9601734916a33fd04ead98016ad0bc4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17913
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/jecht/romstage.c')
| -rw-r--r-- | src/mainboard/google/jecht/romstage.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 2d19b26d6296..a71d3fe53c09 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -25,11 +25,9 @@ #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> #include <mainboard/google/jecht/spd/spd.h> -#include "gpio.h" +#include <variant/gpio.h> +#include "onboard.h" -#define DUMMY_DEV PNP_DEV(0x2e, 0) -#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) void mainboard_romstage_entry(struct romstage_params *rp) { @@ -53,7 +51,11 @@ void mainboard_romstage_entry(struct romstage_params *rp) void mainboard_pre_console_init(void) { /* Early SuperIO setup */ - it8772f_ac_resume_southbridge(DUMMY_DEV); - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV); + ite_kill_watchdog(IT8772F_GPIO_DEV); + ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Turn On Power LED */ + set_power_led(LED_ON); + } |