google/jecht: add new mainboard

Taken from CrOS, including everything up to commit da4c33913.
Adapted to upstream.

Change-Id: I095e6726a220200ba17719fc05fcdc521da484e8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10432
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 63 insertions, 0 deletions

diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c
new file mode 100644
index 000000000000..756381ef3ff6
--- /dev/null
+++ b/src/mainboard/google/jecht/romstage.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <string.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/romstage.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8772f/it8772f.h>
+#include <mainboard/google/jecht/spd/spd.h>
+#include "gpio.h"
+
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
+#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
+
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+	struct pei_data pei_data;
+
+	post_code(0x32);
+
+	/* Initialize GPIOs */
+	init_gpios(mainboard_gpio_config);
+
+	/* Fill out PEI DATA */
+	memset(&pei_data, 0, sizeof(pei_data));
+	mainboard_fill_pei_data(&pei_data);
+	mainboard_fill_spd_data(&pei_data);
+	rp->pei_data = &pei_data;
+
+	/* Call into the real romstage main with this board's attributes. */
+	romstage_common(rp);
+}
+
+void mainboard_pre_console_init(void)
+{
+	/* Early SuperIO setup */
+	it8772f_ac_resume_southbridge(DUMMY_DEV);
+	ite_kill_watchdog(GPIO_DEV);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}