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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-22 16:59:44 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-15 17:57:33 +0000 |
| commit | e43972474c0eebc478722f7c371a8c68318f24cf (patch) | |
| tree | 34abf5f2a18cb350fe4871b4e8509c5da4705d37 /src/mainboard/google/jecht/romstage.c | |
| parent | 4d56a0625516ba436903d59d9c0a4a13827d89be (diff) | |
| download | coreboot-e43972474c0eebc478722f7c371a8c68318f24cf.tar.gz coreboot-e43972474c0eebc478722f7c371a8c68318f24cf.tar.bz2 coreboot-e43972474c0eebc478722f7c371a8c68318f24cf.zip | |
soc/intel/broadwell: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables
bootblock console by default.
Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/google/jecht/romstage.c')
| -rw-r--r-- | src/mainboard/google/jecht/romstage.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 86888c82f885..4fc2ba0c93be 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -39,15 +39,3 @@ void mainboard_post_raminit(struct romstage_params *rp) if (CONFIG(CHROMEOS)) init_bootmode_straps(); } - -void mainboard_pre_console_init(void) -{ - /* Early SuperIO setup */ - it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV); - ite_kill_watchdog(IT8772F_GPIO_DEV); - ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Turn On Power LED */ - set_power_led(LED_ON); - -} |