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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-09-25 10:11:50 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-10 18:23:11 +0000 |
| commit | 3f6c400310a930d226e85e77f29c51f03578f0f1 (patch) | |
| tree | c5166f00656f7bdfec54200262f139aef1e59c95 /src/mainboard/google/kahlee/OemCustomize.c | |
| parent | 4af2342673befb65b19363c9265a0887ff001eec (diff) | |
| download | coreboot-3f6c400310a930d226e85e77f29c51f03578f0f1.tar.gz coreboot-3f6c400310a930d226e85e77f29c51f03578f0f1.tar.bz2 coreboot-3f6c400310a930d226e85e77f29c51f03578f0f1.zip | |
google/kahlee: Add defines in OemCustomize.c
Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max
supported for the device. AGESA's DRAM procedures follow the BKDG and
may vary depending on the number of slots on the motherboard. DIMM
numbering and ordering is also affected by this value.
Replace hardcoded integers with defined values for DIMM slots and
number of channels.
Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21853
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/kahlee/OemCustomize.c')
| -rw-r--r-- | src/mainboard/google/kahlee/OemCustomize.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 36bb419d417d..bd58e0ecc8e7 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -13,14 +13,20 @@ * GNU General Public License for more details. */ +#include <chip.h> #include <AGESA.h> #include <agesawrapper.h> #include <PlatformMemoryConfiguration.h> +#define DIMMS_PER_CHANNEL 1 +#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH +#error "Too many DIMM sockets defined for the mainboard" +#endif + static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), MOTHER_BOARD_LAYERS(LAYERS_6), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), |