mainboard/google/kahlee: Update PCIe port map

- Grunt moved the EMMC chip to port 2, where Kahlee had the SD reader on
PCIe port 1, so move the OemCustomize file into the variant directory.
- Add comments in baseboard version so it's easier to understand.
- Update reset pins, put the definitions in gpio.h

BUG=b:70255003
TEST=Build and boot Kahlee.  Build Grunt.

Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

1 files changed, 0 insertions, 125 deletions

diff --git a/src/mainboard/google/kahlee/bootblock/OemCustomize.c b/src/mainboard/google/kahlee/bootblock/OemCustomize.c
deleted file mode 100644
index 0551184b1817..000000000000
--- a/src/mainboard/google/kahlee/bootblock/OemCustomize.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <agesawrapper.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	/* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
-				2, 1,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0x04, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
-				2, 2,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0x2, 0)
-	},
-	/* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) for Card Reader */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
-				2, 3,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0x3, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for NC */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
-				2, 4,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
-				2, 5,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0, 0)
-	},
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	/* DDI0 - eDP */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
-	},
-	/* DDI1 - DP */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-	},
-	/* DDI2 - DP */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
-	},
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = (void *)PortList,
-	.DdiLinkList  = (void *)DdiList
-};
-
-/*---------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This is the stub function will call the host environment through the
- *    binary block interface (call-out port) to provide a user hook opportunity.
- *
- *  Parameters:
- *    @param[in]      **PeiServices
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------*/
-VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
-	InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
-	InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
-}