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| author | Huayang Duan <huayang.duan@mediatek.com> | 2019-04-08 20:10:23 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 09:57:52 +0000 |
| commit | 42b7b77571bd45f28850eb66a17f0ef91f995f28 (patch) | |
| tree | 1b86bbd805ecd312c285ab92ba4bea3cd8f2eff3 /src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c | |
| parent | b8f65ad68a0ce722012ff4fac39e2b18f0025fbe (diff) | |
| download | coreboot-42b7b77571bd45f28850eb66a17f0ef91f995f28.tar.gz coreboot-42b7b77571bd45f28850eb66a17f0ef91f995f28.tar.bz2 coreboot-42b7b77571bd45f28850eb66a17f0ef91f995f28.zip | |
mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup
Support SAMSUNG KMDP6001DA-B425 and MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR
From the calibration log of MICRON MT29VZZZAD8DQKSL, we found
the begin pass range of RX window earlier than with other DDR type.
So need change the DQS starting offset to increase the scan range of RX window.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c')
| -rw-r--r-- | src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c new file mode 100644 index 000000000000..512023b35eb9 --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/emi.h> + +struct sdram_params params = { + .impedance = { + [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, + [ODT_ON] = {0xA, 0x9, 0x0, 0xE} + }, + .wr_level = { + [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, + [CHANNEL_B] = { {0x21, 0x28}, {0x21, 0x29} } + }, + .cbt_cs = { + [CHANNEL_A] = {0x2, 0x2}, + [CHANNEL_B] = {0x2, 0x2} + }, + .cbt_mr12 = { + [CHANNEL_A] = {0x5E, 0x5E}, + [CHANNEL_B] = {0x5E, 0x5C} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; |