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| author | Matt DeVillier <matt.devillier@gmail.com> | 2022-12-17 11:45:40 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-21 13:38:06 +0000 |
| commit | 53bf72b131d68216b589306ab68b787a6de4c18c (patch) | |
| tree | f8ce831f8266214c81ead30b7ce6240d02882db5 /src/mainboard/google/octopus/variants/baseboard/gpio.c | |
| parent | 0822ce8b08aa96c74a3d1a0d6b717c019924e8c3 (diff) | |
| download | coreboot-53bf72b131d68216b589306ab68b787a6de4c18c.tar.gz coreboot-53bf72b131d68216b589306ab68b787a6de4c18c.tar.bz2 coreboot-53bf72b131d68216b589306ab68b787a6de4c18c.zip | |
mb/google/octopus: Add method to set GPIOs in romstage
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.
TEST=tested with rest of patch train
Change-Id: I4a8e11945ae64b000051989089e0ebae22896c6b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70905
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/octopus/variants/baseboard/gpio.c')
| -rw-r--r-- | src/mainboard/google/octopus/variants/baseboard/gpio.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 2238a9ffdae6..60431c2faf01 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -377,6 +377,13 @@ variant_sleep_gpio_table(size_t *num, int slp_typ) return sleep_gpio_table; } +const struct pad_config *__weak +variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(PAD_SCC(GPIO_PCH_WP), GPIO_COMM_SCC_NAME), |