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| author | Marco Chen <marcochen@chromium.org> | 2019-07-10 13:13:45 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-16 16:34:40 +0000 |
| commit | af62855ac4aa0fde702b94769f14966609bedb20 (patch) | |
| tree | 8f61f91955350c66a441cdb87635fed19f1baba5 /src/mainboard/google/octopus/variants/baseboard/gpio.c | |
| parent | 9b0f93347249cf260fe7db0072131277b846cc1a (diff) | |
| download | coreboot-af62855ac4aa0fde702b94769f14966609bedb20.tar.gz coreboot-af62855ac4aa0fde702b94769f14966609bedb20.tar.bz2 coreboot-af62855ac4aa0fde702b94769f14966609bedb20.zip | |
mb/google/octopus/variants/garg: support LTE power sequence
GPIOs related to power sequnce are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:137033609
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Change-Id: I7bf6fee087c885c22363b44aa98aa61f91be90b4
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/octopus/variants/baseboard/gpio.c')
| -rw-r--r-- | src/mainboard/google/octopus/variants/baseboard/gpio.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 82f4ee1618ff..b3145d10dfcb 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -331,6 +331,19 @@ static const struct pad_config early_gpio_table[] = { */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, ENPU), /* ESPI_IO1 */ + + /* GPIO_67 and GPIO_117 are in early_gpio_table and gpio_table. For variants + * having LTE SKUs, these two GPIOs would be overridden to output high first + * in the bootblock then be set to default state in gpio_table for non-LTE + * SKUs and keep to output high for LTE SKUs in ramstage. + */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ + /* GPIO_161 is in early_gpio_table and gpio_table because LTE SKU needs + * to override this pin to output low then high respectively in two + * stages. + */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ }; const struct pad_config *__weak |