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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-01-11 07:46:50 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-01-12 18:03:23 +0100 |
| commit | 6d6298dddc4147e7a1df6c51cb97b3d94e9c4584 (patch) | |
| tree | e51953d0c3691a6ae4ff491981d7e77f0d3aff7a /src/mainboard/google/parrot/devicetree.cb | |
| parent | 2dd601efafb54433e1bbf60f3936eeba7ef353e2 (diff) | |
| download | coreboot-6d6298dddc4147e7a1df6c51cb97b3d94e9c4584.tar.gz coreboot-6d6298dddc4147e7a1df6c51cb97b3d94e9c4584.tar.bz2 coreboot-6d6298dddc4147e7a1df6c51cb97b3d94e9c4584.zip | |
ibexpeak / bd82x6x: Make SATA mode user-visible option.
Ability to choose compatibility mode is interesting for testing payloads and
OS for compatibility with older systems.
As per comments
"ide_legacy_combined # TODO: Does nothing since
generations, remove from sb code?"
The "combined" mode was removed. It wasn't used by any mobo and the code for
it is almost identical to IDE one other than few bits relating to interrupt
handling and ISA mode.
Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4658
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/parrot/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/parrot/devicetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index cd65fbf9a401..59586cc784cc 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -61,8 +61,6 @@ chip northbridge/intel/sandybridge register "gpi8_routing" = "1" register "gpi15_routing" = "1" #lid switch gpe - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" # EC range is 0xFD60 (EC_IO) and 0x68/0x6C |