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| author | Shelley Chen <shchen@google.com> | 2018-10-22 18:07:04 -0700 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2018-10-29 16:49:43 +0000 |
| commit | bf00401e8a4d58c2717ae0d9d45ea5a0114b0990 (patch) | |
| tree | 0e47b40612ca4b79d09e6f9426530622eedeb00d /src/mainboard/google/poppy/romstage.c | |
| parent | 6cc937e687d8761bcdf26a0b5a122c392238d10c (diff) | |
| download | coreboot-bf00401e8a4d58c2717ae0d9d45ea5a0114b0990.tar.gz coreboot-bf00401e8a4d58c2717ae0d9d45ea5a0114b0990.tar.bz2 coreboot-bf00401e8a4d58c2717ae0d9d45ea5a0114b0990.zip | |
mb/google/poppy/variants/nami: Add field to identify single channel DDR
Variants of Nami need to accommodate single channel DDR. Will use
GPP_D10 on nami for identification. GPP_D10 will return 1 when device
is using single channel DDR and 0 when using dual channel DDR.
BUG=b:117194353
BRANCH=None
TEST=dmidecode | grep Channel and make sure that the correct number of
channels gets returned.
Change-Id: If86ab2c5404c4e818ce496ea935227ab5e51730a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/poppy/romstage.c')
| -rw-r--r-- | src/mainboard/google/poppy/romstage.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index bac1e17889ed..9de1602a1a53 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -171,7 +171,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) memcpy(&mem_cfg->RcompTarget, p.rcomp_target, p.rcomp_target_size); mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(p.type, p.use_sec_spd); - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + if (p.single_channel) + mem_cfg->MemorySpdPtr10 = 0; + else + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; mem_cfg->MemorySpdDataLen = spd_info[p.type].len; mem_cfg->SaOcSupport = p.enable_sa_oc_support; |