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authorMarvin Evers <marvin.evers@stud.hs-bochum.de>2023-12-04 02:28:25 +0100
committerMatt DeVillier <matt.devillier@gmail.com>2024-01-17 20:47:43 +0000
commit059476d18c8e8e09fa5a42b1db24b965fa08f71a (patch)
tree97dca72a79dbc94a24d9be7ee7ed2d2bf953fce7 /src/mainboard/google/poppy/variants/atlas/devicetree.cb
parent6e5cc4ce7c6228aa245796e818ec00124c4e9f4a (diff)
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mb/google/poppy: Use chipset dt reference names
Use the references from the chipset devicetree as this makes the comments superfluous. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/google/poppy/variants/atlas/devicetree.cb')
-rw-r--r--src/mainboard/google/poppy/variants/atlas/devicetree.cb110
1 files changed, 55 insertions, 55 deletions
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 4ba644fb40c5..eb7d660ad58e 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -229,12 +229,12 @@ chip soc/intel/skylake
device cpu_cluster 0 on end
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 on end # SA thermal subsystem
- device pci 05.0 on end # SA IMGU
- device pci 13.0 off end # Integrated Sensor Hub
- device pci 14.0 on
+ device ref system_agent on end
+ device ref igpu on end
+ device ref sa_thermal on end
+ device ref imgu on end
+ device ref ish off end
+ device ref south_xhci on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
@@ -257,11 +257,11 @@ chip soc/intel/skylake
end
end
end
- end # USB xHCI
- device pci 14.1 on end # USB xDCI (OTG)
- device pci 14.2 on end # Thermal Subsystem
- device pci 14.3 on end # Camera
- device pci 15.0 on
+ end
+ device ref south_xdci on end
+ device ref thermal on end
+ device ref cio on end
+ device ref i2c0 on
chip drivers/i2c/hid
register "generic.hid" = ""ACPI0C50""
register "generic.desc" = ""STM Touchscreen""
@@ -277,9 +277,9 @@ chip soc/intel/skylake
register "hid_desc_reg_offset" = "0xab"
device i2c 0x49 on end
end
- end # I2C #0 - Touchscreen
- device pci 15.1 off end # I2C #1
- device pci 15.2 on
+ end
+ device ref i2c1 off end
+ device ref i2c2 on
chip drivers/i2c/hid
register "generic.hid" = ""ACPI0C50""
register "generic.desc" = ""ELAN Touchpad""
@@ -288,17 +288,17 @@ chip soc/intel/skylake
register "hid_desc_reg_offset" = "0x01"
device i2c 0x15 on end
end
- end # I2C #2 - Trackpad
- device pci 15.3 on end # I2C #3 - Camera
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 17.0 off end # SATA
- device pci 19.0 on end # UART #2
- device pci 19.1 off end # I2C #5
- device pci 19.2 on
+ end
+ device ref i2c3 on end # Camera
+ device ref heci1 on end
+ device ref heci2 off end
+ device ref csme_ider off end
+ device ref csme_ktr off end
+ device ref heci3 off end
+ device ref sata off end
+ device ref uart2 on end
+ device ref i2c5 off end
+ device ref i2c4 on
chip drivers/i2c/max98373
register "vmon_slot_no" = "4"
register "imon_slot_no" = "5"
@@ -332,48 +332,48 @@ chip soc/intel/skylake
register "mic_amp_in_sel" = ""diff""
device i2c 1a on end
end
- end # I2C #4 - Audio
- device pci 1c.0 on
+ end
+ device ref pcie_rp1 on
chip drivers/wifi/generic
register "wake" = "GPE0_DW1_07" # GPP_B7
device pci 00.0 on end
end
- end # PCI Express Port 1
- device pci 1c.1 off end # PCI Express Port 2
- device pci 1c.2 off end # PCI Express Port 3
- device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 off end # PCI Express Port 5
- device pci 1c.5 off end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 off end # PCI Express Port 9
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1e.0 on end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 on
+ end
+ device ref pcie_rp2 off end
+ device ref pcie_rp3 off end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 off end
+ device ref pcie_rp6 off end
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref pcie_rp9 off end
+ device ref pcie_rp10 off end
+ device ref pcie_rp11 off end
+ device ref pcie_rp12 off end
+ device ref uart0 on end
+ device ref uart1 off end
+ device ref gspi0 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
device spi 0 on end
end
- end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1e.4 on end # eMMC
- device pci 1e.5 off end # SDIO
- device pci 1e.6 off end # SDCard
- device pci 1f.0 on
+ end
+ device ref gspi1 off end
+ device ref emmc on end
+ device ref sdio off end
+ device ref sdxc off end
+ device ref lpc_espi on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
- end # LPC Interface
- device pci 1f.1 on end # P2SB
- device pci 1f.2 on end # Power Management Controller
- device pci 1f.3 on end # Intel HDA
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
+ end
+ device ref p2sb on end
+ device ref pmc on end
+ device ref hda on end
+ device ref smbus on end
+ device ref fast_spi on end
+ device ref gbe off end
end
end