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| author | Matt DeVillier <matt.devillier@gmail.com> | 2022-09-07 17:21:01 -0500 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-09-22 15:35:19 +0000 |
| commit | 45b1da33c80a4b1328794a5a59c93d1988cee4f1 (patch) | |
| tree | 7f7c7c6b7c44632c72b2a5bc717f74bcf678f7c8 /src/mainboard/google/puff/chromeos-32MiB.fmd | |
| parent | 826b45b69b9dd492771798679d3a8223a954217f (diff) | |
| download | coreboot-45b1da33c80a4b1328794a5a59c93d1988cee4f1.tar.gz coreboot-45b1da33c80a4b1328794a5a59c93d1988cee4f1.tar.bz2 coreboot-45b1da33c80a4b1328794a5a59c93d1988cee4f1.zip | |
mb/google/hatch: split up hatch and puff baseboards
The hatch and puff baseboards have diverged enough to where it makes
more sense to split them into separate boards. Copy the mb/google/hatch
directory into a new dir 'puff' and strip out all boards and items
related to the hatch baseboard. Remove all puff-related items from the
original hatch directory. Clean up and alphabetize Kconfig selections.
Test: build and boot akemi hatch variant and wyvern puff variant.
Change-Id: I8c7350f3afcff3ddefc6fa14054a3f9257568cd3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62970
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/puff/chromeos-32MiB.fmd')
| -rw-r--r-- | src/mainboard/google/puff/chromeos-32MiB.fmd | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/src/mainboard/google/puff/chromeos-32MiB.fmd b/src/mainboard/google/puff/chromeos-32MiB.fmd new file mode 100644 index 000000000000..81840b1e6074 --- /dev/null +++ b/src/mainboard/google/puff/chromeos-32MiB.fmd @@ -0,0 +1,48 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x300000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x2ff000 + } + SI_BIOS@0x300000 0x1d00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0x1000000 + RW_SECTION_A@0x1000000 0x460000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x44ffc0 + RW_FWID_A@0x45ffc0 0x40 + } + RW_SECTION_B@0x1460000 0x460000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x44ffc0 + RW_FWID_B@0x45ffc0 0x40 + } + RW_MISC@0x18c0000 0x40000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } + RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x38000 0x2000 + RW_NVRAM(PRESERVE)@0x3a000 0x5000 + RW_SPD_CACHE(PRESERVE)@0x3f000 0x1000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x1900000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} |