diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-11-07 11:19:34 -0600 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-06 17:18:54 +0200 |
| commit | 84da959c691a1efa87ff47edd03d5427eaf6e093 (patch) | |
| tree | 0f0b307667c992a4f2596cdb08f77e927f93c28e /src/mainboard/google/rambi/ec.h | |
| parent | fa91e02a15ff45f70886b969a9587468afec10ac (diff) | |
| download | coreboot-84da959c691a1efa87ff47edd03d5427eaf6e093.tar.gz coreboot-84da959c691a1efa87ff47edd03d5427eaf6e093.tar.bz2 coreboot-84da959c691a1efa87ff47edd03d5427eaf6e093.zip | |
rambi: update EC support
Fix the SMI and SCI gpios for Rambi. Also, add in the
EC callbacks for the SMI handler. Note that the handler
for GPI SMIs has not been tested yet as baytrail chipset
code doesn't yet support setting up those configurations
yet.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Noted that SCI was enabled in /sys/firmware/acpi/interrupts
for the EC's SCI GPI. Also was able to see Chrome EC messages
with CONFIG_DEBUG_SMI and powering down at the dev screen.
Change-Id: I67b278fd38e1c09271d2c1e16e42f6e8c49e3a70
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176077
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4948
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/google/rambi/ec.h')
| -rw-r--r-- | src/mainboard/google/rambi/ec.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/rambi/ec.h b/src/mainboard/google/rambi/ec.h index c55a5045641c..bd98b2acbc75 100644 --- a/src/mainboard/google/rambi/ec.h +++ b/src/mainboard/google/rambi/ec.h @@ -22,9 +22,10 @@ #include <ec/google/chromeec/ec_commands.h> -/* TODO(adurbin): Need to figure out how to handle 2 sets of GPIO banks. */ -#define EC_SCI_GPI 0 /* GPIO_SC_0 is EC_SCI# */ -#define EC_SMI_GPI 7 /* GPIO_SSUS_7 is EC_SMI# */ +/* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */ +#define EC_SCI_GPI 24 +/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */ +#define EC_SMI_GPI 23 #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ |