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| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-08-01 13:05:14 -0500 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-08-01 22:23:54 +0000 |
| commit | 3044af7adc652f41670f8de0c3c54bc09f632079 (patch) | |
| tree | f1b936af303292c7e3ed35a188809fbc3f9a249a /src/mainboard/google/rambi/variants/squawks | |
| parent | 9fe248fbeca2c62153dc4d8d89bfc9cd1d84dcd3 (diff) | |
| download | coreboot-3044af7adc652f41670f8de0c3c54bc09f632079.tar.gz coreboot-3044af7adc652f41670f8de0c3c54bc09f632079.tar.bz2 coreboot-3044af7adc652f41670f8de0c3c54bc09f632079.zip | |
mb/google,samsung/*: Add LPC TPM chip driver to devicetree
With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code]
and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing
TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver
(drivers/pc80/tpm) must be added to devicetree in order to ensure the
new acpigen code is used to replace it.
Test: boot various google/samsung boards, verify SSDT created with
LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux
Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27786
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/rambi/variants/squawks')
| -rw-r--r-- | src/mainboard/google/rambi/variants/squawks/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/rambi/variants/squawks/devicetree.cb b/src/mainboard/google/rambi/variants/squawks/devicetree.cb index 46f23850827c..ae4bfe510358 100644 --- a/src/mainboard/google/rambi/variants/squawks/devicetree.cb +++ b/src/mainboard/google/rambi/variants/squawks/devicetree.cb @@ -85,6 +85,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the |