mb/google/rex: Refactor baseboard/variant gpio pad configuration

This patch tries to simplify the baseboard/variant GPIO programming
starting with Google/Rex. The idea is to let each variant maintain
its own complete GPIO PAD configuration table instead of having a
back-and-forth call between baseboard and variants.

With this patch coreboot performing GPIO programming is now much
simpler where the common code block calls into respective variants
and gets the gpio table prior to the pad configuration.

BUG=b:238165977 (Simplify baseboard/variant GPIO programming starting
                 with Google/Rex)
TEST=Able to build and boot the Google/Rex board.
AP firmware log with DEBUG_GPIO kconfig lists the early GPIOs being
configured from the `rex0` variant.

gpio_padcfg [0xd3, 08] DW0 [0x44000300 : 0x40000400 : 0x40000400]
gpio_padcfg [0xd3, 08] DW1 [0x00000020 : 0x00000000 : 0x00000020]
gpio_padcfg [0xd3, 08] DW2 [0x00000000 : 0x00000000 : 0x00000000]
gpio_padcfg [0xd3, 08] DW3 [0x00000000 : 0x00000000 : 0x00000000]
gpio_padcfg [0xd3, 09] DW0 [0x44000300 : 0x40000400 : 0x40000400]
gpio_padcfg [0xd3, 09] DW1 [0x00000021 : 0x00000000 : 0x00000021]
gpio_padcfg [0xd3, 09] DW2 [0x00000000 : 0x00000000 : 0x00000000]
gpio_padcfg [0xd3, 09] DW3 [0x00000000 : 0x00000000 : 0x00000000]

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8ec5c6991ec90a3884464e7f15f33327bfe4839a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

1 files changed, 52 insertions, 0 deletions

diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c
new file mode 100644
index 000000000000..c25cb25bdcce
--- /dev/null
+++ b/src/mainboard/google/rex/variants/rex0/gpio.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* ToDo: Fill gpio configuration */
+	/* H08 : UART0_RXD ==> UART_DBG_TX_SOC_RX */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* H09 : UART0_TXD ==> UART_DBG_RX_SOC_TX */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* ToDo: Fill early gpio configuration */
+	/* H08 : UART0_RXD ==> UART_DBG_TX_SOC_RX */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* H09 : UART0_TXD ==> UART_DBG_RX_SOC_TX */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* ToDo: Fill romstage gpio configuration */
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Create the stub for romstage gpio, typically use for power sequence */
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+};
+
+DECLARE_WEAK_CROS_GPIOS(cros_gpios);