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| author | Subrata Banik <subratabanik@google.com> | 2022-08-08 18:13:35 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-08-12 08:17:32 +0000 |
| commit | 52398d6474add678c195fefd1d9a7e533ef39e30 (patch) | |
| tree | 473b263d7f9e69813225bc64ec50f6ed1906be4d /src/mainboard/google/rex | |
| parent | 50c73b5d46d31796082a440049652cc30d26af42 (diff) | |
| download | coreboot-52398d6474add678c195fefd1d9a7e533ef39e30.tar.gz coreboot-52398d6474add678c195fefd1d9a7e533ef39e30.tar.bz2 coreboot-52398d6474add678c195fefd1d9a7e533ef39e30.zip | |
mb/google/rex: Describe USB2/3 ports in devicetree
This patch describes the USB2/3 ports in devicetree to generate ACPI
code at runtime. The ACPI code includes the port definition, location,
type information.
BUG=b:224325352
TEST=Able to build and boot MTLRVP.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7d787a9986099852d6a0d193bbc28487bf430fe4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66542
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/rex')
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/overridetree.cb | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 7fa8dbdf2a5e..b3442b4dc2ea 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -141,6 +141,56 @@ chip soc/intel/meteorlake device generic 0 on end end end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B01)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on end + end + end + end + end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" |