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| author | Subrata Banik <subratabanik@google.com> | 2022-07-12 09:41:00 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-14 12:40:52 +0000 |
| commit | 691af099c8f7e593636d8a62265307ddc2976f6f (patch) | |
| tree | 5d988ba3866fde41f505cb3ba2667228b7616887 /src/mainboard/google/rex | |
| parent | 4c350eedbe3f95f9c78fb6b67c838b5d48dcc7f9 (diff) | |
| download | coreboot-691af099c8f7e593636d8a62265307ddc2976f6f.tar.gz coreboot-691af099c8f7e593636d8a62265307ddc2976f6f.tar.bz2 coreboot-691af099c8f7e593636d8a62265307ddc2976f6f.zip | |
mb/google/rex: Add chip config for I2C devices
+-----------+--------------------+-------------+--------+
| INTERFACE | PCI Number (B:D:F) | DEVICE | Speed |
+-----------+--------------------+-------------+--------+
| LPSS I2C0 | 0:0x15:0 | WFC | 400KHz |
| | +-------------+--------+
| | | AUDIO_DB | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C1 | 0:0x15:1 | Touch Panel | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C2 | 0:0x15:2 | NC | NC |
+-----------+--------------------+-------------+--------+
| LPSS I2C3 | 0:0x15:3 | Touch Pad | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C4 | 0:0x19:0 | TPM | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C5 | 0:0x19:1 | UFC | 400KHz |
| | +-------------+--------+
| | | SAR1 | 400KHz |
| | +-------------+--------+
| | | SAR2 | 400KHz |
| | +-------------+--------+
| | | HPS | 400KHz |
+-----------+--------------------+-------------+--------+
BUG=b:224325352
TEST=Able to build Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I76a28f175372542d441c787deb2a096382658ace
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/mainboard/google/rex')
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/overridetree.cb | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 62b831b97be8..730af8bb30a9 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -1,4 +1,60 @@ chip soc/intel/meteorlake + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio and WFC | + #| I2C1 | Touchscreen | + #| I2C3 | Touchpad | + #| I2C4 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C5 | UFC, SAR1, SAR2, HPS | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[4] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 900, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + device domain 0 on device ref pcie_rp9 on # Enable SSD Card PCIE 9 using clk 4 |