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| author | Subrata Banik <subrata.banik@intel.com> | 2020-01-03 14:50:49 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-01-09 08:25:12 +0000 |
| commit | d5be4e4046a1ef89672f57e8c5674f95b66c97ae (patch) | |
| tree | 82bade23e9466ead8bcaad73f0f0da6bccc061cc /src/mainboard/google/sarien/dsdt.asl | |
| parent | a8280e4cc0bf146ca29030a8d1d50b7276d26c6e (diff) | |
| download | coreboot-d5be4e4046a1ef89672f57e8c5674f95b66c97ae.tar.gz coreboot-d5be4e4046a1ef89672f57e8c5674f95b66c97ae.tar.bz2 coreboot-d5be4e4046a1ef89672f57e8c5674f95b66c97ae.zip | |
soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi
This patch creates a common instance of northbridge.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to
refer northbridge.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
Device(MCHC) presence after booting to OS.
Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/sarien/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/sarien/dsdt.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index a809b75e01ed..c32470eb1bc8 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -36,7 +36,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } /* Per board variant mainboard hooks. */ |