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| author | Jon Murphy <jpmurphy@google.com> | 2022-02-17 20:40:23 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-28 13:30:58 +0000 |
| commit | ee67ddc707fddbff30ecb173f7854f930eb63a92 (patch) | |
| tree | 44f3371e6128fc4eab8b742cbbef4e4469f44648 /src/mainboard/google/skyrim/variants/baseboard/devicetree.cb | |
| parent | 4f4f32ba2083e7a32858c0e49130f5646c9d94a8 (diff) | |
| download | coreboot-ee67ddc707fddbff30ecb173f7854f930eb63a92.tar.gz coreboot-ee67ddc707fddbff30ecb173f7854f930eb63a92.tar.bz2 coreboot-ee67ddc707fddbff30ecb173f7854f930eb63a92.zip | |
mb/google/skyrim: Add eSPI configuration
BUG=b:214413613
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If1177dda705738222ce7f6f42dceafb14d37c98c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard/google/skyrim/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/skyrim/variants/baseboard/devicetree.cb | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 242f0fac7274..a3440735c16a 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -1,5 +1,43 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip soc/amd/sabrina + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x62, + /* + * Only 0x62 and 0x66 are required. But, this is not supported by + * standard IO decodes and there are only 4 generic I/O windows + * available. Hence, open a window from 0x62-0x67. + */ + .size = 5, + }, + .generic_io_range[1] = { + .base = 0x800, /* EC_HOST_CMD_REGION0 */ + .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ + }, + .generic_io_range[2] = { + .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ + .size = 255, /* EC_MEMMAP_SIZE */ + }, + .generic_io_range[3] = { + .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ + .size = 8, /* 0x200 - 0x207 */ + }, + + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_IN_BAND, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 0, + .flash_ch_en = 0, + + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), + }" + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" |