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| author | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2022-09-23 14:25:41 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-28 21:29:59 +0000 |
| commit | cfec5ddc1605d0cb91449e556d2064f27b42adc0 (patch) | |
| tree | ad53d5c24b39a1b109ba21e0aefa34e69e56451c /src/mainboard/google/skyrim/variants/baseboard/gpio.c | |
| parent | 4236e2a23a0ad0dffc98322d961e65719158738f (diff) | |
| download | coreboot-cfec5ddc1605d0cb91449e556d2064f27b42adc0.tar.gz coreboot-cfec5ddc1605d0cb91449e556d2064f27b42adc0.tar.bz2 coreboot-cfec5ddc1605d0cb91449e556d2064f27b42adc0.zip | |
mb/google/skyrim: Rename pcie_gpio_table to romstage_gpio_table
Rename so table more indicative of when GPIOs are set, and so it can
be used for more than just setting PCIe GPIOs.
Rename the getter function to match.
Change-Id: I285602209072247895c2cb0830f3faf675328757
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/google/skyrim/variants/baseboard/gpio.c')
| -rw-r--r-- | src/mainboard/google/skyrim/variants/baseboard/gpio.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index 1a9e5d1ffe0b..b234a5dee3c0 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -188,8 +188,9 @@ static const struct soc_amd_gpio early_gpio_table[] = { PAD_GPO(GPIO_9, HIGH), }; -/* PCIE_RST needs to be brought high before FSP-M runs */ -static const struct soc_amd_gpio pcie_gpio_table[] = { +/* Romstage GPIO configuration */ +static const struct soc_amd_gpio romstage_gpio_table[] = { + /* PCIE_RST needs to be brought high before FSP-M runs */ /* Deassert all AUX_RESET lines & PCIE_RST */ /* WLAN_AUX_RESET_L (ACTIVE LOW) */ PAD_GPO(GPIO_7, HIGH), @@ -201,10 +202,10 @@ static const struct soc_amd_gpio pcie_gpio_table[] = { PAD_GPO(GPIO_6, HIGH), }; -__weak void variant_pcie_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +__weak void variant_romstage_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) { - *size = ARRAY_SIZE(pcie_gpio_table); - *gpio = pcie_gpio_table; + *size = ARRAY_SIZE(romstage_gpio_table); + *gpio = romstage_gpio_table; } void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) |