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| author | Martin Roth <gaumless@gmail.com> | 2023-03-03 16:38:25 -0700 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-03-09 17:55:55 +0000 |
| commit | d4712010107eab9e6ae897a7912d4407f299eecc (patch) | |
| tree | 6677fca70d9a3b75a3863ed9dfb824287a68ee1f /src/mainboard/google/skyrim/variants/baseboard/gpio.c | |
| parent | 5b2d6735ff91b266c350c68e6226be2be45e8e6b (diff) | |
| download | coreboot-d4712010107eab9e6ae897a7912d4407f299eecc.tar.gz coreboot-d4712010107eab9e6ae897a7912d4407f299eecc.tar.bz2 coreboot-d4712010107eab9e6ae897a7912d4407f299eecc.zip | |
mb/google/skyrim: override winterhold PCIe config
Winterhold boards populate either NVMe or eMMC, but not both.
This means that there is always one link that is unpopulated. The PCIe
configuration code takes longer to verify that a link is unpopulated
than to just train the link, so this slows down the boot by roughly
80ms vs the case when the device is present. Not training the device
at all lowers boot time by another 20ms, for a total of 100ms saved.
Looking at the NVMe CLKREQ signal before initializing the ports allows
us to identify which device is populated and only initialize that
device.
BUG=b:271569628
TEST=Boot Whiterun and eMMC or NVMe correctly work, boot time is lower.
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0b87f5e968cd1c87e62a1c0fbdee1fc0723f655d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/skyrim/variants/baseboard/gpio.c')
| -rw-r--r-- | src/mainboard/google/skyrim/variants/baseboard/gpio.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index cef3338cccdb..932acaaee605 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -201,6 +201,8 @@ static const struct soc_amd_gpio romstage_gpio_table[] = { PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), /* SSD_AUX_RESET_L */ PAD_GPO(GPIO_6, HIGH), + /* CLK_REQ0_L / SSD */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), /* Enable touchscreen, hold in reset */ /* EN_PP3300_TCHSCR */ PAD_GPO(GPIO_131, HIGH), |