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| author | Tim Van Patten <timvp@google.com> | 2022-09-06 09:56:52 -0600 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-09-19 09:54:40 +0000 |
| commit | cf9e0a08f584d47c8e6c2e3148e07d9cffe4be7f (patch) | |
| tree | af41ca42d14a0f3968d443d5b0bc772c97a4eb2c /src/mainboard/google/skyrim/variants/skyrim | |
| parent | b06873f77cba236c766a38fe58115a956c600397 (diff) | |
| download | coreboot-cf9e0a08f584d47c8e6c2e3148e07d9cffe4be7f.tar.gz coreboot-cf9e0a08f584d47c8e6c2e3148e07d9cffe4be7f.tar.bz2 coreboot-cf9e0a08f584d47c8e6c2e3148e07d9cffe4be7f.zip | |
mb/google/skyrim: Add "Normal" DPTC values
Add the Normal Mode DPTC values for Skyrim.
These values were generated by AMD.
BRANCH=none
BUG=b:217911928
TEST=Build skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I1e1f55b941f3e70aad33d55a90fb012eac3ba12d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67690
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/skyrim/variants/skyrim')
| -rw-r--r-- | src/mainboard/google/skyrim/variants/skyrim/overridetree.cb | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb index 95e3090dc081..a9896510b1c8 100644 --- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -245,4 +245,16 @@ chip soc/amd/mendocino end end # UART1 + # Normal + # These registers are defined in AMD DevHub document #57316. + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "275" + register "sustained_power_limit_mW" = "15000" + register "thermctl_limit_degreeC" = "100" + register "vrm_current_limit_mA" = "28000" + register "vrm_maximum_current_limit_mA" = "50000" + register "vrm_soc_current_limit_mA" = "10000" + end # chip soc/amd/mendocino |