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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-03-18 16:57:22 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-19 18:27:05 +0000 |
| commit | 5b51faaaea48adf49429d4bfb96d88d9e5d9e08c (patch) | |
| tree | 4a1d790fb96e4d3d4f92192042bddfb9e78e9f67 /src/mainboard/google/skyrim/variants | |
| parent | b9ee6f351b4552f024edee3f1e1d72a4a09ec45a (diff) | |
| download | coreboot-5b51faaaea48adf49429d4bfb96d88d9e5d9e08c.tar.gz coreboot-5b51faaaea48adf49429d4bfb96d88d9e5d9e08c.tar.bz2 coreboot-5b51faaaea48adf49429d4bfb96d88d9e5d9e08c.zip | |
mb/google/skyrim/devicetree: set PSPP policy to DXIO_PSPP_DISABLED
Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, PSPP will be reenabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ea602596acb8e5ea92076386e80102c3bc757af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Diffstat (limited to 'src/mainboard/google/skyrim/variants')
| -rw-r--r-- | src/mainboard/google/skyrim/variants/baseboard/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 7d4fb7f549db..03bb55eee86f 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -47,6 +47,8 @@ chip soc/amd/sabrina register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works + device domain 0 on device ref lpc_bridge on chip ec/google/chromeec |