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| author | Keith Hui <buurin@gmail.com> | 2023-07-22 12:49:05 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-13 20:31:23 +0000 |
| commit | 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da (patch) | |
| tree | 8b0fb3b07ecb3cfa84aa77b51c0e1053a1415c73 /src/mainboard/google/stout/devicetree.cb | |
| parent | 940fe080bf1ed2dac827b569c70fb0ea11496041 (diff) | |
| download | coreboot-45e4ab4a660cb7ce312f2d11a153f2d9ef4158da.tar.gz coreboot-45e4ab4a660cb7ce312f2d11a153f2d9ef4158da.tar.bz2 coreboot-45e4ab4a660cb7ce312f2d11a153f2d9ef4158da.zip | |
mb/*: Update SPD mapping for sandybridge boards
Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.
Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.
Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/mainboard/google/stout/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/stout/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index a2b8452d9952..8fd19fce5876 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -17,6 +17,7 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" register "ec_present" = "1" # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" |