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| author | Nico Huber <nico.h@gmx.de> | 2019-11-17 02:58:00 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:52:24 +0000 |
| commit | 47bf4986815407393c1cf02922c882ed0f336bb2 (patch) | |
| tree | 210fdf4d4a0bafdc5aed1356a40f1f42c6293df9 /src/mainboard/google/stout/early_init.c | |
| parent | 6760e0bdcd37e904c121800652cd2ac3920d9cd9 (diff) | |
| download | coreboot-47bf4986815407393c1cf02922c882ed0f336bb2.tar.gz coreboot-47bf4986815407393c1cf02922c882ed0f336bb2.tar.bz2 coreboot-47bf4986815407393c1cf02922c882ed0f336bb2.zip | |
nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree
Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid
probing by the MRC. We can do that for all boards instead, based on the
devicetree setting.
Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/google/stout/early_init.c')
| -rw-r--r-- | src/mainboard/google/stout/early_init.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 94d409297c81..754bec60bb98 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -32,8 +32,6 @@ void mainboard_late_rcba_config(void) { - u32 reg32; - /* * GFX INTA -> PIRQA (MSI) * D20IP_XHCI XHCI INTA -> PIRQD (MSI) @@ -71,12 +69,6 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; } /* |