Add google/veyron_jerry board

This is essentially a copy of veyron_pinky for now.

BUG=chrome-os-partner:33269
TEST=build and boot

Change-Id: I151c82f54ece4620953d0db5aedf027a3293926f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 267611f2354be4384de3f05d2459a4e421ee6b4f
Original-Change-Id: I0d473361e0850ee3b11da5a809f8396826ccdad6
Original-Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225301
Reviewed-on: http://review.coreboot.org/9544
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 126 insertions, 0 deletions

diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c
new file mode 100644
index 000000000000..b050228b5ff0
--- /dev/null
+++ b/src/mainboard/google/veyron_jerry/romstage.c
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/cache.h>
+#include <arch/exception.h>
+#include <arch/stages.h>
+#include <armv7.h>
+#include <assert.h>
+#include <cbfs.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <delay.h>
+#include <program_loading.h>
+#include <soc/sdram.h>
+#include <soc/clock.h>
+#include <soc/pwm.h>
+#include <soc/grf.h>
+#include <soc/tsadc.h>
+#include <stdlib.h>
+#include <symbols.h>
+#include <timestamp.h>
+#include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "timer.h"
+
+static void regulate_vdd_log(unsigned int mv)
+{
+	unsigned int duty_ns;
+	const u32 period_ns = 2000;	/* pwm period: 2000ns */
+	const u32 max_regulator_mv = 1350;	/* 1.35V */
+	const u32 min_regulator_mv = 870;	/* 0.87V */
+
+	writel(IOMUX_PWM1, &rk3288_grf->iomux_pwm1);
+
+	assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
+
+	duty_ns = (max_regulator_mv - mv) * period_ns /
+			(max_regulator_mv - min_regulator_mv);
+
+	pwm_init(1, period_ns, duty_ns);
+}
+
+static void configure_l2ctlr(void)
+{
+	uint32_t l2ctlr;
+
+	l2ctlr = read_l2ctlr();
+	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
+
+	/*
+	* Data RAM write latency: 2 cycles
+	* Data RAM read latency: 2 cycles
+	* Data RAM setup latency: 1 cycle
+	* Tag RAM write latency: 1 cycle
+	* Tag RAM read latency: 1 cycle
+	* Tag RAM setup latency: 1 cycle
+	*/
+	l2ctlr |= (1 << 3 | 1 << 0);
+	write_l2ctlr(l2ctlr);
+}
+
+void main(void)
+{
+#if CONFIG_COLLECT_TIMESTAMPS
+	uint64_t start_romstage_time;
+	uint64_t before_dram_time;
+	uint64_t after_dram_time;
+	uint64_t base_time = timestamp_get();
+	start_romstage_time = timestamp_get();
+#endif
+
+	console_init();
+	configure_l2ctlr();
+	tsadc_init();
+
+	/* vdd_log 1200mv is enough for ddr run 666Mhz */
+	regulate_vdd_log(1200);
+#if CONFIG_COLLECT_TIMESTAMPS
+	before_dram_time = timestamp_get();
+#endif
+	sdram_init(get_sdram_config());
+#if CONFIG_COLLECT_TIMESTAMPS
+	after_dram_time = timestamp_get();
+#endif
+
+	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
+	mmu_config_range((uintptr_t)_dram/MiB,
+			 CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK);
+	mmu_config_range((uintptr_t)_dma_coherent/MiB,
+			 _dma_coherent_size/MiB, DCACHE_OFF);
+
+	cbmem_initialize_empty();
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_init(base_time);
+	timestamp_add(TS_START_ROMSTAGE, start_romstage_time);
+	timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
+	timestamp_add(TS_AFTER_INITRAM, after_dram_time);
+	timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+
+#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE)
+	void *entry = vboot2_load_ramstage();
+	if (entry != NULL)
+		stage_exit(entry);
+#endif
+
+	run_ramstage();
+}