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| author | Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> | 2020-11-23 15:40:57 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-11-25 18:40:24 +0000 |
| commit | 1856effaf2397edc3e00b8c2cf2acdb9f6bd935e (patch) | |
| tree | 63f1fd2a34897d01dce79cf9a27bdf333abc7c73 /src/mainboard/google/volteer/variants/eldrid | |
| parent | 2f1d686ba64a255dfde99d50f16f60805b31d7cc (diff) | |
| download | coreboot-1856effaf2397edc3e00b8c2cf2acdb9f6bd935e.tar.gz coreboot-1856effaf2397edc3e00b8c2cf2acdb9f6bd935e.tar.bz2 coreboot-1856effaf2397edc3e00b8c2cf2acdb9f6bd935e.zip | |
mb/google/volteer: Update Eldrid USB2 port settings in overridetree
1. Disable M.2 WWAN and Type-A Port A1
2. Change register 4 to 3 and tuning USB2 Port1 eye diagram
3. Lower camera driving
BUG=b:169105751
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I6b8a5c0d5e814de232d79a43354f5ec0220fc5ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants/eldrid')
| -rw-r--r-- | src/mainboard/google/volteer/variants/eldrid/overridetree.cb | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 72571c039a7f..51bc99159b25 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -58,12 +58,22 @@ chip soc/intel/tigerlake }, }, }" - #These settings improve the USB2 Port1 eye diagram + + #Disable Type-A Port A1 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" + + #Disable M.2 WWAN + register "usb2_ports[2]" = "USB2_PORT_EMPTY" + + #improve the USB2 Port1 eye diagram + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" + + #lower camera driving register "usb2_ports[4]" = "{ .enable = 1, - .tx_bias = 7, - .tx_emp_enable = 7, - .pre_emp_bias = 3, + .tx_bias = 0, + .tx_emp_enable = 0, + .pre_emp_bias = 0, .pre_emp_bit = 0, }" |