diff options
| author | Felix Singer <felixsinger@posteo.net> | 2021-07-12 13:53:53 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-07-17 00:10:08 +0000 |
| commit | 5f235b0a3f3d12abd3556d593b352babe022ce32 (patch) | |
| tree | 296855192ebd605ea7ae16089d3449cf37b20eb4 /src/mainboard/google/volteer | |
| parent | ea192f86c98d68e00c1421edd2478784b95998a4 (diff) | |
| download | coreboot-5f235b0a3f3d12abd3556d593b352babe022ce32.tar.gz coreboot-5f235b0a3f3d12abd3556d593b352babe022ce32.tar.bz2 coreboot-5f235b0a3f3d12abd3556d593b352babe022ce32.zip | |
mb/google/volteer/baseboard: Configure chipset_lockdown separately
The configuration of the setting `chipset_lockdown` doesn't have any
effect for most of the variants since their configuration of
`common_soc_config` overwrites the configuration of the baseboard's
devicetree. If `chipset_lockdown` is configured separately in the
baseboard devicetree, the variant overridetrees reuse its
configuration.
Thus, move `chipset_lockdown` out of `common_soc_config` in the
baseboard devicetree and configure it separately.
Change-Id: I595c042cf62680d61f60965710d382bfdcd81671
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56209
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/volteer')
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 915553a10597..e2a84f81380f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -325,8 +325,8 @@ chip soc/intel/tigerlake #| I2C3 | Camera, SAR1 | #| I2C5 | Trackpad | #+-------------------+---------------------------+ + register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[0] = { .speed_mhz = 1, .early_init = 1, |