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| author | Nick Vaccaro <nvaccaro@google.com> | 2021-06-11 11:31:18 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-06-14 17:46:22 +0000 |
| commit | fae935a7c571d1e769a3f74361d3669ee11a3aaa (patch) | |
| tree | 3bde55b9c651ef5e3b303f9c4a0795babea6b10d /src/mainboard/google/volteer | |
| parent | 369a30de781c825c9851c683ca49e53e5bee18de (diff) | |
| download | coreboot-fae935a7c571d1e769a3f74361d3669ee11a3aaa.tar.gz coreboot-fae935a7c571d1e769a3f74361d3669ee11a3aaa.tar.bz2 coreboot-fae935a7c571d1e769a3f74361d3669ee11a3aaa.zip | |
mb/google/volteer/var/voxel: change GPP_B2 to PLTRST
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang.
BUG=b:174776411
BRANCH=none
TEST=none
Change-Id: Ia7db2d0a1fff98d1cfb8e7e979c0a81b9f3d0e9e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/volteer')
| -rw-r--r-- | src/mainboard/google/volteer/variants/voxel/gpio.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/volteer/variants/voxel/gpio.c b/src/mainboard/google/volteer/variants/voxel/gpio.c index 4ec02c5167a0..c74d14d77098 100644 --- a/src/mainboard/google/volteer/variants/voxel/gpio.c +++ b/src/mainboard/google/volteer/variants/voxel/gpio.c @@ -25,7 +25,7 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* B2 : VRALERT# ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_B2, 1, DEEP), + PAD_CFG_GPO(GPP_B2, 1, PLTRST), /* B3 : CPU_GP2 ==> PEN_DET_ODL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B3, NONE, PLTRST), /* B5 : ISH_I2C0_CVF_SDA */ @@ -248,7 +248,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_A17, NONE, DEEP), /* B2 : VRALERT# ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_B2, 1, DEEP), + PAD_CFG_GPO(GPP_B2, 1, PLTRST), /* B11 : PMCALERT# ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ |