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| author | Matt Papageorge <matthewpapa07@gmail.com> | 2020-07-30 15:32:34 -0500 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-08-28 17:54:19 +0000 |
| commit | 48b2b2b8c14a6dcc79a4cb2974ef90370586e1a4 (patch) | |
| tree | cef610c5cab03a4cac8698acf1eaa4fb1f8b6fb0 /src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb | |
| parent | b87effe1dde3cc3f81a6afef073009ba808e11a7 (diff) | |
| download | coreboot-48b2b2b8c14a6dcc79a4cb2974ef90370586e1a4.tar.gz coreboot-48b2b2b8c14a6dcc79a4cb2974ef90370586e1a4.tar.bz2 coreboot-48b2b2b8c14a6dcc79a4cb2974ef90370586e1a4.zip | |
mb/google/zork: Disable SATA device for all Zork platforms to save power
SATA is currently turned on in the Dalboz and Trembyle base board
variant devicetrees, even though no Google/Zork device uses SATA; for
mass storage they either use eMMC or NVME PCIe SSDs. This patch disables
both the SATA PCIe device and the bus where it was the only enabled
device on. The next patch in this patch train sets a new FSP-M UPD
setting
BUG=b:162302027
Change-Id: Ie7773d9dcb0518c3e01bdd0af23b62268ab64694
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44068
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 5a86b1cb5d26..c7616020ffd8 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -286,8 +286,8 @@ chip soc/amd/picasso device pci 0.6 off end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 8.2 on # Internal GPP Bridge 0 to Bus B - device pci 0.0 on end # AHCI + device pci 8.2 off # Internal GPP Bridge 0 to Bus B + device pci 0.0 off end # AHCI end device pci 14.0 on end # SM device pci 14.3 on # - D14F3 bridge |