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| author | Zheng Bao <fishbaozi@gmail.com> | 2020-10-27 15:36:55 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-11-06 13:02:24 +0000 |
| commit | 795d73c6d851fde143041483af5dff7c448febe6 (patch) | |
| tree | a44a592eebe49f10e82bf5d07861d69bd663f5d1 /src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb | |
| parent | 0cae9008f01af3cd89dad317d42292c04b53bb51 (diff) | |
| download | coreboot-795d73c6d851fde143041483af5dff7c448febe6.tar.gz coreboot-795d73c6d851fde143041483af5dff7c448febe6.tar.bz2 coreboot-795d73c6d851fde143041483af5dff7c448febe6.zip | |
soc/amd/picasso: Update coreboot UPD variable names to include units
Use command below to change the variable globally.
sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \
--exclude-dir=build --exclude-dir=crossgcc`
BUG=b:171334623
TEST=Build
Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 58e25e6ba3af..9f5ef0c37b9f 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -15,22 +15,22 @@ chip soc/amd/picasso # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time - register "prochot_l_deassertion_ramp_time" = "20" #mS + register "prochot_l_deassertion_ramp_time_ms" = "20" # Lower die temperature limit - register "thermctl_limit" = "100" #degrees C + register "thermctl_limit_degreeC" = "100" # FP5 Processor Voltage Supply PSI Currents - register "psi0_current_limit" = "18000" #mA - register "psi0_soc_current_limit" = "12000" #mA - register "vddcr_soc_voltage_margin" = "0" #mV - register "vddcr_vdd_voltage_margin" = "0" #mV + register "psi0_current_limit_mA" = "18000" + register "psi0_soc_current_limit_mA" = "12000" + register "vddcr_soc_voltage_margin_mV" = "0" + register "vddcr_vdd_voltage_margin_mV" = "0" # VRM Limits - register "vrm_maximum_current_limit" = "0" #mA - register "vrm_soc_maximum_current_limit" = "0" #mA - register "vrm_current_limit" = "0" #mA - register "vrm_soc_current_limit" = "0" #mA + register "vrm_maximum_current_limit_mA" = "0" + register "vrm_soc_maximum_current_limit_mA" = "0" + register "vrm_current_limit_mA" = "0" + register "vrm_soc_current_limit_mA" = "0" # Misc SMU settings register "sb_tsi_alert_comparator_mode_en" = "0" |