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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-13 02:36:02 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-06-01 20:37:04 +0000 |
| commit | c4eb45fa85d9860ce94829c6c977b9e28a297bf9 (patch) | |
| tree | 4b1f29ce8cf52e878ee54e16127f685e53ac7f31 /src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb | |
| parent | db4b21a1d04678041fae73be4a700f393cee879d (diff) | |
| download | coreboot-c4eb45fa85d9860ce94829c6c977b9e28a297bf9.tar.gz coreboot-c4eb45fa85d9860ce94829c6c977b9e28a297bf9.tar.bz2 coreboot-c4eb45fa85d9860ce94829c6c977b9e28a297bf9.zip | |
soc/amd/picasso: introduce and use chipset device tree
The chipset devicetree only has the essential PCIe devices enabled that
are needed for the SoC code to work. It also defines aliases for all
PCIe devices that can be used to reference the devices in the mainboard-
specific devicetrees and devicetree overrides. To make the change easier
to review that part will be done in a follow-up patch.
Despite missing in the PPR, device pci 18.7 exists on Picasso.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b7c3fd32579a23539594672593a243172c161c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 252540093c80..0d0e8299ca96 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -252,17 +252,10 @@ chip soc/amd/picasso register "pspp_policy" = "DXIO_PSPP_POWERSAVE" - device cpu_cluster 0 on - device lapic 0 on end - end - # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.0 on end # Root Complex device pci 0.2 on end # IOMMU - device pci 1.0 on end # Dummy Host Bridge, must be enabled - device pci 1.1 off end # GPP Bridge 0 device pci 1.2 on # GPP Bridge 1 - Wifi chip drivers/wifi/generic register "wake" = "GEVENT_8" @@ -270,9 +263,6 @@ chip soc/amd/picasso end end device pci 1.3 on end # GPP Bridge 2 - SD - device pci 1.4 off end # GPP Bridge 3 - device pci 1.5 off end # GPP Bridge 4 - device pci 8.0 on end # Dummy Host Bridge, must be enabled device pci 8.1 on # Internal GPP Bridge 0 to Bus A device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA @@ -363,10 +353,6 @@ chip soc/amd/picasso device pci 0.6 off end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 8.2 off # Internal GPP Bridge 0 to Bus B - device pci 0.0 off end # AHCI - end - device pci 14.0 on end # SM device pci 14.3 on # - D14F3 bridge chip ec/google/chromeec device pnp 0c09.0 on @@ -398,13 +384,6 @@ chip soc/amd/picasso end end end - device pci 18.0 on end # Data fabric [0-7] - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end end # domain device mmio 0xfedc5000 on |