diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-07-21 17:09:31 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-07-23 13:47:39 +0000 |
| commit | 86db2c74ffc38ad6ca92c62f0fb2858a2423c089 (patch) | |
| tree | 546f8cc26eda84d97d2eff47c07defebe9393db4 /src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c | |
| parent | a19d98647b0b1862c28b362505b30f4551b2fe2c (diff) | |
| download | coreboot-86db2c74ffc38ad6ca92c62f0fb2858a2423c089.tar.gz coreboot-86db2c74ffc38ad6ca92c62f0fb2858a2423c089.tar.bz2 coreboot-86db2c74ffc38ad6ca92c62f0fb2858a2423c089.zip | |
amd/picasso: rename PCIe descriptor to DXIO descriptor
Most of the DXIO descriptors are used to configure PCIe engines and
lanes, but on Picasso system some of the DXIO lanes can also be
configured as SATA or XGBE ports.
Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c index 82a11b05fbc2..8d55db6934f2 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c @@ -4,16 +4,16 @@ #include <baseboard/variants.h> #include <commonlib/bsd/compiler.h> -void __weak variant_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_descs, - size_t *pcie_num, +void __weak variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); } -static const fsp_pcie_descriptor pcie_descriptors[] = { +static const fsp_dxio_descriptor dxio_descriptors[] = { { // NVME SSD .port_present = true, @@ -60,10 +60,10 @@ static const fsp_pcie_descriptor pcie_descriptors[] = { } }; -const fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num) +const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num) { - *num = ARRAY_SIZE(pcie_descriptors); - return pcie_descriptors; + *num = ARRAY_SIZE(dxio_descriptors); + return dxio_descriptors; } const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) |