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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-07-20 15:46:56 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-07-23 13:46:40 +0000 |
| commit | a19d98647b0b1862c28b362505b30f4551b2fe2c (patch) | |
| tree | 48c2975b0cd46c5933156b9f334babf10d1bf8ff /src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c | |
| parent | a2b04f45c0f8383cf8d6f5ea513d1598c23e822c (diff) | |
| download | coreboot-a19d98647b0b1862c28b362505b30f4551b2fe2c.tar.gz coreboot-a19d98647b0b1862c28b362505b30f4551b2fe2c.tar.bz2 coreboot-a19d98647b0b1862c28b362505b30f4551b2fe2c.zip | |
vc/amd/fsp/picasso: add logical to lane number in port descriptor struct
The lane numbers in the PCIe/DXIO descriptor are the logical and not the
physical ones, so add logical to the corresponding field names of the
fsp_pcie_descriptor struct.
Change-Id: I7037fed225119218e87593932815aff815e83ff8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c index df42f6b87e7d..9e82684442d2 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c @@ -23,8 +23,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { // NVME SSD .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 0, - .end_lane = 3, + .start_logical_lane = 0, + .end_logical_lane = 3, .device_number = 1, .function_number = 7, .link_aspm = ASPM_L1, @@ -37,8 +37,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { // WLAN .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 4, - .end_lane = 4, + .start_logical_lane = 4, + .end_logical_lane = 4, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, @@ -52,8 +52,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { // SD Reader .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 5, - .end_lane = 5, + .start_logical_lane = 5, + .end_logical_lane = 5, .device_number = 1, .function_number = 3, .link_aspm = ASPM_L1, @@ -69,8 +69,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = { // NVME SSD .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = NVME_START_LANE, - .end_lane = NVME_END_LANE, + .start_logical_lane = NVME_START_LANE, + .end_logical_lane = NVME_END_LANE, .device_number = 1, .function_number = 7, .link_aspm = ASPM_L1, @@ -84,8 +84,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = { // WLAN .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = WLAN_START_LANE, - .end_lane = WLAN_END_LANE, + .start_logical_lane = WLAN_START_LANE, + .end_logical_lane = WLAN_END_LANE, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, @@ -99,8 +99,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = { // SD Reader .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = SD_START_LANE, - .end_lane = SD_END_LANE, + .start_logical_lane = SD_START_LANE, + .end_logical_lane = SD_END_LANE, .device_number = 1, .function_number = 3, .link_aspm = ASPM_L1, |