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| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2020-06-10 19:05:45 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-11 23:03:18 +0000 |
| commit | ca428c3027cde0844daf823a7621db254ba23ba8 (patch) | |
| tree | 9331e2b9cf8ed940ffa6c02a9316f25b385ed581 /src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c | |
| parent | 4d58083703726443e712541be42eb3ec264caea8 (diff) | |
| download | coreboot-ca428c3027cde0844daf823a7621db254ba23ba8.tar.gz coreboot-ca428c3027cde0844daf823a7621db254ba23ba8.tar.bz2 coreboot-ca428c3027cde0844daf823a7621db254ba23ba8.zip | |
vc/amd/fsp/platform_descriptors: drop prefix from PCIe/DDI structs
The picasso_ prefix on the fsp_pcie_descriptor and fsp_ddi_descriptor
structs isn't needed, since this code is picasso-specific, so drop it.
Change-Id: Ia6a0ddb411aa64becc3c23a876f2ea43cb68e028
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42252
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c index fb96ff2537cd..f5f4842ed0cd 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c @@ -5,9 +5,9 @@ #include <commonlib/bsd/compiler.h> #include <soc/soc_util.h> -void __weak variant_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs, +void __weak variant_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, - const picasso_fsp_ddi_descriptor **ddi_descs, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); @@ -18,7 +18,7 @@ void __weak variant_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor * * Type 1 parts, while reporting as Picasso through cpuid, are fused like a Dali. * Those parts need to be configured as Type 2. */ -static const picasso_fsp_pcie_descriptor pco_pcie_descriptors[] = { +static const fsp_pcie_descriptor pco_pcie_descriptors[] = { { // NVME SSD .port_present = true, @@ -64,7 +64,7 @@ static const picasso_fsp_pcie_descriptor pco_pcie_descriptors[] = { } }; -static const picasso_fsp_pcie_descriptor dali_pcie_descriptors[] = { +static const fsp_pcie_descriptor dali_pcie_descriptors[] = { { // NVME SSD .port_present = true, @@ -111,7 +111,7 @@ static const picasso_fsp_pcie_descriptor dali_pcie_descriptors[] = { } }; -const picasso_fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num) +const fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num) { /* Type 2 or Type 1 fused like Type 2. */ if (soc_is_dali()) { @@ -125,7 +125,7 @@ const picasso_fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num) } -static const picasso_fsp_ddi_descriptor pco_ddi_descriptors[] = { +static const fsp_ddi_descriptor pco_ddi_descriptors[] = { { // DDI0, DP0, eDP .connector_type = EDP, @@ -152,7 +152,7 @@ static const picasso_fsp_ddi_descriptor pco_ddi_descriptors[] = { } }; -static const picasso_fsp_ddi_descriptor dali_ddi_descriptors[] = { +static const fsp_ddi_descriptor dali_ddi_descriptors[] = { { // DDI0, DP0, eDP .connector_type = EDP, @@ -173,7 +173,7 @@ static const picasso_fsp_ddi_descriptor dali_ddi_descriptors[] = { } }; -const picasso_fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) +const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) { /* Type 2 or Type 1 fused like Type 2. */ if (soc_is_dali()) { |